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參數(shù)資料
| 型號： | SY605JC TR |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 2/8頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DELAY LINE 255TAP 28-PLCC |
| 標(biāo)準包裝： | 750 |
| 標(biāo)片/步級數(shù)： | 255 |
| 功能： | 可編程 |
| 延遲到第一抽頭： | 4ns |
| 接頭增量： | 15.7ps |
| 可用的總延遲： | 4ns ~ 40ns |
| 獨立延遲數(shù)： | 1 |
| 電源電壓： | 4.2 V ~ 5.7 V |
| 工作溫度： | 0°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 28-PLCC |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | SY605JCTR SY605JCTR-ND |
2
SY605
Micrel
FUNCTIONAL DESCRIPTION
The output pulse generation cycle begins with the arrival of
TRIG shown in Figure 1. The DAC values are latched by the
rising edge of WRITE. Then, when TRIG transitions to a high
and CE is low the linear ramp is initiated.
Figure 1.
D0 – D7
Data input pins (ECL compatible). On the falling edge of
WRITE, D0 - D7 are latched into the DAC input register. D0
is the LSB. These inputs specify the amount of delay from the
rising edge of TRIG to the output pulse.
WRITE, WRITE
Differential write inputs (ECL compatible).
These inputs
control the parallel data input latch. When WRITE is a logical
one, the data latch is transparent. Data is latched on the falling
edge of WRITE.
A single-ended write may be used by
connecting WRITE to VBB.
CE
Chip enable input (ECL compatible). CE must be a logical
zero on the rising edge of TRIG to enable the device to
respond to the trigger. If CE is floating, the trigger will always
be enabled.
TRIG, TRIG
Differential trigger inputs (ECL compatible). The rising edge
of TRIG is used to trigger the delay cycle if CE is a logical zero.
If CE is a logical one, no operation occurs. It is recommended
that triggering be performed with differential inputs.
PIN DESCRIPTION
OUT, OUT
Differential outputs (ECL compatible).
IEXT
Current reference pin. The amount of current sourced into this
pin determines the span of output delay. The voltage at IEXT
is typically –1.25V.
COMP1, COMP2
Compensation pins.
A 0.1
F ceramic capacitor must be
connected between COMP1 and VEE0, and COMP2 and VEE0
(see Figure 3).
VEE
Device power. All VEE pins must be connected.
VCC
Device ground. All VCC pins must be connected together.
VBB
A –1.36V (typical) output.
When
the
ramp
level reaches that of the DAC, the
comparator initiates the pulse generator to produce an output
pulse resets the ramp and the cycle is ready to begin again.
CE
TRIG
OUT
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| SY605JZ | 功能描述:IC DELAY LINE 255TAP 28-PLCC RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 延遲線 系列:- 標(biāo)準包裝:2,500 系列:- 標(biāo)片/步級數(shù):- 功能:多個，不可編程 延遲到第一抽頭:10ns 接頭增量:- 可用的總延遲:10ns 獨立延遲數(shù):4 電源電壓:4.75 V ~ 5.25 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:14-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:14-SOIC 包裝:帶卷 (TR) |
| SY605JZ TR | 功能描述:IC DELAY LINE 255TAP 28-PLCC RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 延遲線 系列:- 標(biāo)準包裝:2,500 系列:- 標(biāo)片/步級數(shù):- 功能:多個，不可編程 延遲到第一抽頭:10ns 接頭增量:- 可用的總延遲:10ns 獨立延遲數(shù):4 電源電壓:4.75 V ~ 5.25 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:14-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:14-SOIC 包裝:帶卷 (TR) |
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