參數(shù)資料
型號: SY58606U
廠商: Micrel Semiconductor,Inc.
英文描述: 4.25Gbps Precision, 1:2 CML Fanout Buffer with Internal Termination and Fail Safe Input
中文描述: 4.25Gbps的精密,1:2扇出緩沖器白血病與內(nèi)部的終止和故障安全輸入
文件頁數(shù): 5/13頁
文件大?。?/td> 667K
代理商: SY58606U
Micrel, Inc.
SY58606U
AC Electrical Characteristics
V
CC
= +2.5V ±5% or +3.3V ±10%, R
L
= 100
across the outputs, Input t
r
/t
f
: <300ps; T
A
= –40°C to +85°C, unless
otherwise stated.
September 2006
5
M9999-092606-A
hbwhelp@micrel.com
or (408) 955-1690
Symbol
Parameter
Condition
Min
Typ
Max
Units
NRZ Data
4.25
Gbps
f
MAX
Maximum Frequency
V
OUT
> 200mV Clock
V
IN
: 100mV-200mV
V
IN
: 200mV-800mV
Note 8
2.5
3.0
GHz
150
270
400
ps
t
PD
Propagation Delay IN-to-Q
120
220
320
ps
Within Device Skew
3
15
ps
t
Skew
Part-to-Part Skew
Note 9
100
ps
Data Random Jitter
Note 10
1
ps
RMS
ps
PP
ps
RMS
ps
PP
Deterministic Jitter
Note 11
10
Clock Cycle-to-Cycle Jitter
Note 12
1
t
Jitter
Total Jitter
Note 13
10
t
R
t
F
Output Rise/Fall Times
(20% to 80%)
At full output swing.
30
50
85
ps
Duty Cycle
Differential I/O
47
53
%
Notes:
8.
9.
Within device skew is measured between two different outputs under identical input transitions.
Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and no skew at the edges at the
respective inputs.
10. Random jitter is measured with a K28.7 pattern, measured at
f
MAX
.
11. Deterministic jitter is measured at 2.5Gbps with both K28.5 and 2
23
–1 PRBS pattern.
12. Cycle-to-cycle jitter definition: the variation period between adjacent cycles over a random sample of adjacent cycle pairs. t
JITTER
_
CC
= T
n
–T
n+1
,
where T is the time between rising edges of the output signal.
13. Total jitter definition: with an ideal clock input frequency of
f
MAX
(device), no more than one output edge in 10
12
output edges will deviate by
more than the specified peak-to-peak jitter value.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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