參數(shù)資料
型號: SY58605UMGTR
廠商: MICREL INC
元件分類: 時鐘及定時
英文描述: 3.2Gbps Precision, LVDS Buffer with Internal Termination and Fail Safe Input
中文描述: 58605 SERIES, LOW SKEW CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC8
封裝: 2 X 2 MM, LEAD FREE, MLF-8
文件頁數(shù): 5/12頁
文件大?。?/td> 636K
代理商: SY58605UMGTR
Micrel, Inc.
SY58605U
AC Electrical Characteristics
V
CC
= +2.5V ±5%, R
L
= 100
across the outputs, Input t
r
/t
f
: <300ps; T
A
= –40°C to +85°C, unless otherwise stated.
September 2006
5
M9999-092606-A
hbwhelp@micrel.com
or (408) 955-1690
Symbol
Parameter
Condition
Min
Typ
Max
Units
NRZ Data
3.2
Gbps
f
MAX
Maximum Frequency
V
OUT
> 200mV Clock
V
IN
: 100mV-200mV
200mV-800mV
2.0
3
GHz
170
280
420
ps
t
PD
Propagation Delay IN-to-Q
130
200
300
ps
t
Skew
Part-to-Part Skew
Note 8
135
ps
Data Random Jitter
Note 9
1
ps
RMS
ps
PP
ps
RMS
ps
PP
Deterministic Jitter
Note 10
10
Clock Cycle-to-Cycle Jitter
Note 11
1
t
Jitter
Total Jitter
Note 12
10
t
r,
t
f
Output Rise/Fall Times
(20% to 80%)
At full output swing.
35
60
100
ps
Duty Cycle
Differential I/O
47
53
%
Notes:
8.
Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and no skew at the edges at the
respective inputs.
Random jitter is measured with a K28.7 pattern, measured at
f
MAX
.
10. Deterministic jitter is measured at 2.5Gbps with both K28.5 and 2
23
–1 PRBS pattern.
11. Cycle-to-cycle jitter definition: the variation period between adjacent cycles over a random sample of adjacent cycle pairs. t
JITTER
_
CC
= T
n
–T
n+1
,
where T is the time between rising edges of the output signal.
12. Total jitter definition: with an ideal clock input frequency of
f
MAX
(device), no more than one output edge in 10
12
output edges will deviate by
more than the specified peak-to-peak jitter value.
9.
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