參數(shù)資料
型號: SY58605U
廠商: Micrel Semiconductor,Inc.
英文描述: 3.2Gbps Precision, LVDS Buffer with Internal Termination and Fail Safe Input
中文描述: 3.2Gbps速率精密的LVDS內(nèi)部終端和故障安全輸入緩沖區(qū)
文件頁數(shù): 2/12頁
文件大?。?/td> 636K
代理商: SY58605U
Micrel, Inc.
SY58605U
Ordering Information
(1)
September 2006
2
M9999-092606-A
hbwhelp@micrel.com
or (408) 955-1690
Part Number
Package
Type
Operating
Range
Package Marking
Lead
Finish
SY58605UMG
MLF-8
Industrial
605 with Pb-Free
bar-line indicator
NiPdAu
Pb-Free
SY58605UMGTR
(2)
MLF-8
Industrial
605 with Pb-Free
bar-line indicator
NiPdAu
Pb-Free
Notes:
1. Contact factory for die availability. Dice are guaranteed at T
A
= 25°C, DC Electricals only.
2. Tape and Reel.
Pin Configuration
8-Pin MLF
(MLF-8)
Pin Description
Pin Number
Pin Name
Pin Function
1, 4
IN, /IN
Differential Input: This input pair is the differential signal input to the device. Input
accepts DC-coupled differential signals as small as 100mV
(200mV
PP
). Each pin of
this pair internally terminates with 50
to the VT pin. If the input swing falls below a
certain threshold (typically 30mV), them the Fail Safe Input (FSI) feature will
guarantee a stable output by latching the output to its last valid state. See “Input
Interface Applications” subsection for more details.
2
VT
Input Termination Center-Tap: Each input terminates to this pin. The V
T
pin provides
a center-tap for each input (IN, /IN) to a termination network for maximum interface
flexibility. See “Input Interface Applications” subsection for more details.
3
VREF-AC
Reference Voltage: This output biases to V
CC
–1.2V. It is used for AC-coupling input
IN and /IN. Connect VREF-AC directly to the VT pin. Bypass with 0.01μF low ESR
capacitor to VCC. Maximum sink/source current is ±1.5mA. See “Input Interface
Applications” subsection for more details.
5
GND,
Exposed pad
Ground: Exposed pad must be connected to a ground plane that is the same
potential as the ground pin.
6, 7
/Q, Q
LVDS Differential Output Pair: The output swing is typically 325mV. Normally
terminated with 100
across the pair (Q, /Q). See “LVDS Output Termination”
subsection for more details.
8
VCC
Positive Power Supply: Bypass with 0.1μF//0.01μF low ESR capacitors as close to
the V
CC
pin as possible.
相關(guān)PDF資料
PDF描述
SY58605UMG 3.2Gbps Precision, LVDS Buffer with Internal Termination and Fail Safe Input
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