參數(shù)資料
型號: SY58604UMGTR
廠商: MICREL INC
元件分類: 時鐘及定時
英文描述: 3.2Gbps Precision, LVPECL Buffer with Internal Termination and Fail Safe Input
中文描述: 58604 SERIES, LOW SKEW CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC8
封裝: 2 X 2 MM, LEAD FREE, MLF-8
文件頁數(shù): 5/13頁
文件大小: 664K
代理商: SY58604UMGTR
Micrel, Inc.
SY58604U
AC Electrical Characteristics
V
CC
= +2.5V ±5% or +3.3V ±10%, R
L
= 50
to V
CC
-2V, Input t
r
/t
f
: <300ps; T
A
= –40°C to +85°C, unless otherwise
stated.
September 2006
5
M9999-092606-A
hbwhelp@micrel.com
or (408) 955-1690
Symbol
Parameter
Condition
Min
Typ
Max
Units
NRZ Data
3.2
4.25
Gbps
f
MAX
Maximum Frequency
V
OUT
> 400mV Clock
V
IN
: 100mV-200mV
V
IN
: 200mV-800mV
Note 7
2.5
3
GHz
180
320
450
ps
t
PD
Propagation Delay IN-to-Q
150
230
350
ps
t
Skew
t
Jitter
Part-to-Part Skew
135
ps
Data Random Jitter
Note 8
1
ps
RMS
ps
PP
ps
RMS
ps
PP
Deterministic Jitter
Note 9
10
Clock Cycle-to-Cycle Jitter
Note 10
1
Total Jitter
Note 11
10
t
r,
t
f
Output Rise/Fall Times
(20% to 80%)
At full output swing.
40
75
110
ps
Duty Cycle
Differential I/O
47
53
%
Notes:
7.
Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and no skew at the edges at the
respective inputs.
Random jitter is measured with a K28.7 pattern, measured at
f
MAX
.
Deterministic jitter is measured at 2.5Gbps with both K28.5 and 2
23
–1 PRBS pattern.
10. Cycle-to-cycle jitter definition: the variation period between adjacent cycles over a random sample of adjacent cycle pairs. t
JITTER
_
CC
= T
n
–T
n+1
,
where T is the time between rising edges of the output signal.
11. Total jitter definition: with an ideal clock input frequency of
f
MAX
(device), no more than one output edge in 10
12
output edges will deviate by
more than the specified peak-to-peak jitter value.
8.
9.
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