參數(shù)資料
型號(hào): SY58603UMG
廠商: MICREL INC
元件分類(lèi): 時(shí)鐘及定時(shí)
英文描述: 4.25Gbps Precision CML Buffer with Internal Termination and Fail Safe Input
中文描述: 58603 SERIES, LOW SKEW CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), DSO8
封裝: 2 X 2 MM, LEAD FREE, MLF-8
文件頁(yè)數(shù): 2/13頁(yè)
文件大?。?/td> 680K
代理商: SY58603UMG
Micrel, Inc.
SY58603U
Ordering Information
(1)
September 2006
2
M9999-092206-A
hbwhelp@micrel.com
or (408) 955-1690
Part Number
Package
Type
Operating
Range
Package Marking
Lead
Finish
SY58603UMG
MLF-8
Industrial
603 with Pb-Free
bar-line indicator
NiPdAu
Pb-Free
SY58603UMGTR
(2)
MLF-8
Industrial
603 with Pb-Free
bar-line indicator
NiPdAu
Pb-Free
Notes:
1. Contact factory for die availability. Dice are guaranteed at T
A
= 25°C, DC Electricals only.
2. Tape and Reel.
Pin Configuration
8-Pin MLF
(MLF-8)
Pin Description
Pin Number
Pin Name
Pin Function
1, 4
IN, /IN
Differential Input: This input pair is the differential signal input to the device. Input
accepts DC-Coupled differential signals as small as 100mV
(200mVpp). Each pin of
this pair internally terminates with 50
to the VT pin. If the input swing falls below a
certain threshold (typical 30mV), the Fail Safe Input (FSI) feature will guarantee a
stable output by latching the output to its last valid state. See “Input Interface
Applications” section for more details.
2
VT
Input Termination Center-Tap: Each side of the differential input pair terminates to
VT pin. This pin provides a center-tap to a termination network for maximum
interface flexibility. See “Input Interface Applications” section.
3
VREF-AC
Reference Voltage: This output biases to V
CC
–1.2V. It is used for AC-coupling input
IN and /IN. Connect VREF-AC directly to the corresponding VT pin. Bypass with
0.01μF low ESR capacitor to VCC. Maximum sink/source current is ±1.5mA. Please
refer to the “Input Interface Applications” section for more details.
5
GND
Exposed pad
Ground: Exposed pad must be connected to a ground plane that is the same
potential as the ground pin.
6, 7
/Q, Q
CML Differential Output Pair: Differential buffered output copy of the input signal.
The output swing is typically 400mV. See “CML Output Termination” section.
8
VCC
Positive Power Supply: Bypass with 0.1uF//0.01uF low ESR capacitors as close to
the V
CC
pin as possible.
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