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參數(shù)資料
| 型號： | SY58052UMG |
| 廠商： | MICREL INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | ULTRA-PRECISION CML DATA AND CLOCK SYNCHRONIZER W/ INTERNAL INPUT AND OUTPUT TERMINATION |
| 中文描述： | ATM/SONET/SDH SUPPORT CIRCUIT, QCC16 |
| 封裝： | 3 X 3 MM, LEAD FREE, MLF-16 |
| 文件頁數(shù)： | 2/8頁 |
| 文件大小： | 202K |
| 代理商： | SY58052UMG |
2
Precision Edge
SY58052U
Micrel, Inc.
M9999-020707
hbwhelp@micrel.com or (408) 955-1690
PACKAGE/ORDERING INFORMATION
PIN DESCRIPTION
13
14
15
16
12
11
10
9
1
2
3
4
8
7
6
5
CLK
/CLK
DATA
/DATA
Q
GND
GND
/Q
V
G
G
V
V
/
G
V
16-Pin MLF
(MLF-16)
Pin Number
Pin Name
Pin Function
1, 2
CLK, /CLK
Differential Input: This input pair is the clock signal that re-times the data signal at DATA, /DATA.
Each pin of this pair internally terminates to the V
TCLK
pin to 50
. Note that this input will
default to an indeterminate state if left open. See “Input Interface Applications” section.
3, 4
DATA, /DATA
Differential Input: This input pair is the signal to be synchronized by the CLK, /CLK signal. Each
pin of this pair internally terminates to the V
TD
pin to 50
. Note that this input will default to an
indeterminate state if left open. See “Input Interface Applications” section.
5
VTData
Input Termination Center-Tap: Each of the two inputs, DATA, /DATA terminates to this pin. The
VTData pin provides a center-tap to a termination network for maximum interface flexibility.
See “Input Interface Applications” section.
6
/RESET
TTL/CMOS-Compatible Input: The /RESET input asynchronously forces the Q output to a logic
“0” state whenever it is active low. Possible state changes due to rising edges on CLK, /CLK are
ignored until /RESET goes inactive high.
7, 10, 11, 14, 15
GND
Ground. Exposed pad must be connected to the same potential as the GND pin.
(Exposed Pad)
8, 13
VCC
Positive Power Supply. Bypass with 0.1
μ
F
0.01
μ
F low ESR capacitors.
Differential Output: This CML output pair is the output of the flip-flop. The Data input is
transferred to the Q output at the rising edge of CLK (falling edge of /CLK). See “Input Interface
Applications” section.
12, 9
Q, /Q
16
VTCLK
Input Termination Center-Tap: Each of the two inputs, CLK, /CLK terminates to this pin. The
VTCLK pin provides a center-tap to a termination network for maximum interface flexibility.
See “Input Interface Applications” section.
DATA
/DATA
CLK
/CLK
/RESET
Q
/Q
X
X
X
X
0
0
1
X
X
0
1
1
Q
N–1
Q
N–1
0
/Q
N–1
/Q
N–1
1
X
X
1
0
1
0
1
1
1
0
1
1
0
TRUTH TABLES
Ordering Information
(1)
Package
Type
MLF-16
MLF-16
MLF-16
Operating
Range
Industrial
Industrial
Industrial
Package
Marking
052U
052U
052U with
Lead
Finish
Sn-Pb
Sn-Pb
Pb-Free
NiPdAu
Part Number
SY58052UMI
SY58052UMITR
(2)
SY58052UMG
(3)
Pb-Free bar-line indicator
SY58052UMGTR
(2, 3)
MLF-16
Industrial
052U with
Pb-Free
NiPdAu
Pb-Free bar-line indicator
Notes:
1. Contact factory for die availability. Dice are guaranteed at T
A
= 25
°
C, DC electricals only.
2. Tape and Reel.
3. Pb-Free package recommended for new designs.
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| SY58052UMGTR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:ULTRA-PRECISION CML DATA AND CLOCK SYNCHRONIZER W/ INTERNAL INPUT AND OUTPUT TERMINATION |
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| SY58052UMITR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:ULTRA-PRECISION CML DATA AND CLOCK SYNCHRONIZER W/ INTERNAL INPUT AND OUTPUT TERMINATION |
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