參數(shù)資料
型號(hào): SY58024UMITR
廠商: MICREL INC
元件分類: 運(yùn)動(dòng)控制電子
英文描述: CROSSPOINT SWITCH CML OUTPUTS AND INTERNAL I/O TERMINATION
中文描述: DUAL 2-CHANNEL, CROSS POINT SWITCH, QCC32
封裝: 5 X 5 MM, MLF-32
文件頁(yè)數(shù): 5/11頁(yè)
文件大?。?/td> 132K
代理商: SY58024UMITR
5
Precision Edge
SY58024U
Micrel
M9999-091404
hbwhelp@micrel.com or (408) 955-1690
V
DIFF_IN
,
V
DIFF_OUT
(Typ. 800mV)
Figure 1b. Differential Voltage Swing
V
IN
,
V
OUT
Typ. 400mV
Figure 1a. Single-Ended Voltage Swing
SINGLE-ENDED AND DIFFERENTIAL SWINGS
V
CC
= +2.5V
±
5% or +3.3V
±
10%; R
L
= 100
across each output pair; T
A
=
40
°
C to +85
°
C, unless otherwise stated.
Symbol
Parameter
Condition
Min
Typ
Max
Units
f
MAX
Maximum Operating Frequency
V
IN
100mV; V
OUT
200mV
Clock
6
GHz
NRZ Data
10.7
Gbps
t
pd
Propagation Delay
IN-to-Q
200
350
ps
SEL-to-Q
100
400
ps
t
SKEW
Channel-to-Channel Skew
(Within Bank)
Note 7
20
ps
Part-to-Part Skew
Note 8
75
ps
t
JITTER
Clock
Cycle-to-Cycle Jitter
Note 9
1
ps
rms
Total Jitter
Note 10
10
ps
pp
ps
rms
Data
Random Jitter
Note 11
1
Deterministic Jitter
Note 12
10
ps
pp
ps
rms
Crosstalk Induced Jitter
Adjacent Channel
Note 13
0.7
t
r
, t
f
Output Rise/Fall Time
20% to 80% at full swing.
25
60
ps
Notes:
6. High frequency AC-parameters are guaranteed by design and characterization.
7. Skew is measured between outputs of the same bank under identical transitions.
8. Skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the respective inputs.
9. Cycle-to-cycle jitter definition: The variation of periods between adjacent cycles, T
n
T
n
1
where T is the time between rising edges of the output
signal.
10.Total jitter definition: With an ideal clock input of frequency
f
MAX
, no more than one output edge in 10
12
output edges will deviate by more than the
specified peak-to-peak jitter value.
11.Random jitter is measured with a K28.7 comma detect character pattern, measured at 2.5Gbps
3.2Gbps.
11.Deterministic jitter is measured at 2.5Gbps
3.2Gbps with both K28.5 and 2
23
1 PRBS pattern.
13.Crosstalk induced jitter is defined as the added jitter that results from signals applied to two adjacent channels. It is measured at the output while
applying similar, differential clock frequencies that are asynchronous with respect to each other at inputs.
AC ELECTRICAL CHARACTERISTICS
(6)
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