參數(shù)資料
型號: SY58020UMITR
廠商: MICREL INC
元件分類: 時鐘及定時
英文描述: 6GHz, 1:4 CML FANOUT BUFFER/TRANSLATOR WITH INTERNAL I/O TERMINATION
中文描述: 58020 SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC16
封裝: 3 X 3 MM, MLF-16
文件頁數(shù): 4/9頁
文件大?。?/td> 120K
代理商: SY58020UMITR
4
Precision Edge
SY58020U
Micrel
TIMING DIAGRAM
SINGLE-ENDED AND DIFFERENTIAL SWINGS
V
IN
,
V
OUT
400mV
Figure 1a. Single-Ended Voltage Swing
V
DIFF_IN
,
V
DIFF_OUT
800mV
Figure 1b. Differential Voltage Swing
/IN
IN
/Q
Q
t
pd
V
CC
= 2.5V
±
5% or 3.3V
±
10%; T
A
=
40
°
C to +85
°
C; R
L
= 100
across each output pair or equivalent, unless otherwise stated.
Symbol
Parameter
Condition
Min
Typ
Max
Units
f
MAX
Maximum Operating Frequency
V
OUT
200mV
Clock
6
GHz
NRZ Data
10
Gbps
t
pd
t
CHAN
t
SKEW
t
JITTER
Propagation Delay
110
180
260
ps
Channel-to-Channel Skew
Note 7
4
15
ps
Part-to-Part Skew
Note 8
50
ps
Clock
Cycle-to-Cycle Jitter
Note 9
1
ps(rms)
Total Jitter
Note 10
10
ps(pk-pk)
Data
Random Jitter
Note 11
2.5Gbps
3.2Gbps
1
ps(rms)
Deterministic Jitter
Note 12
2.5Gbps
3.2Gbps
10
ps(pk-pk)
t
r
, t
f
Output Rise/Fall Time 20% to 80%
At full swing
20
40
60
ps
Note 7.
Note 8.
Note 9.
Skew is measured between outputs of the same bank under identical transitions.
Skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the respective inputs.
Cycle-to-cycle jitter definition: The variation of periods between adjacent cycles, T
n
T
n
1
where T is the time between rising edges of the
output signal.
Note 10.
Total jitter definition: With an ideal clock input of frequency
f
MAX
, no more than one output edge in 10
12
output edges will deviate by more
than the specified peak-to-peak jitter value.
Note 11.
Random jitter is measured with a K28.7 comma detect character pattern, measured at 2.5Gbps/3.2Gbps.
Note 12.
Deterministic jitter is measured at 2.5Gbps/3.2Gbps with both K28.5 and 2
23
1 PRBS pattern
AC ELECTRICAL CHARACTERISTICS
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