參數(shù)資料
型號(hào): SY55859LMITR
英文描述: TELECOM SWITCHING CIRCUIT|BIPOLAR|LLCC|32PIN|PLASTIC
中文描述: 電信開(kāi)關(guān)電路|雙極| LLCC | 32腳|塑料
文件頁(yè)數(shù): 2/6頁(yè)
文件大?。?/td> 60K
代理商: SY55859LMITR
2
SuperLite
SY55857L
Micrel
Input Levels
LVDS, CML and HSTL differential signals may be
connected directly to the D inputs. Depending on the actual
worst case voltage seen, performance of SY55857L varies
as per the following table:
Input Voltage
Minimum
Maximum
Range
Voltage Swing
Translation Speed
0 to 2.4V
100mV
2.5Gbps
0 to V
CC +0.3
200mV
1.25Gbps
PIN DESCRIPTIONS
FUNCTIONAL DESCRIPTION
Establishing Static Logic Inputs
Do not leave unused inputs floating. Tie either the true or
complement inputs to ground, but not both. A logic zero is
achieved by connecting the complement input to ground
with the true input floating. For a TTL input, tie a 2.5k
resistor between the complement input and ground. See
“Input Interface” section.
R2
1.5k
R2
1.5k
R1
1.05k
R1
1.05k
GND
DIN
/DIN
VCC
Figure 1. Simplified Input Structure
Pin Number
Pin Name
Description
D0, /D0
1, 2
Channel 0 differential inputs (clock or data). See Figure 1 for input structure.
See “Input Interface” section for typical interface recommendations.
D1, /D1
3, 4
Channel 1 differential inputs (clock or data). See Figure 1 for input structure.
See “Input Interface” section for typical interface recommendations.
Q0, /Q0
9, 8
Channel 0 differential 100k compatible LVPECL outputs. Terminate to
V
CC – 2V. See “LVPECL Output Termination” section. Outputs are low
impedance, emitter-followers. For AC-coupled applications, a pull-down
resistor is required on Q and /Q to ensure a DC current path to GND.
Q1, /Q1
7, 6
Channel 1 differential 100k compatible LVPECL outputs. Terminate to
V
CC – 2V. See “LVPECL Output Termination” section. Outputs are low
impedance, emitter-followers. For AC-coupled applications, a pull-down
resistor is required on Q and /Q to ensure a DC current path to GND.
GND
5
Device ground. Typically connected to Logic ground.
V
CC
10
Supply Voltage. Typically connect to +3.3V
± 10% supply. Bypass with
0.01
F//0.1F low ESR capacitors.
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