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參數(shù)資料
| 型號： | SY10EL38L |
| 廠商： | Micrel Semiconductor,Inc. |
| 英文描述： | 5V/3.3V ÷2 ，÷4/6 Clock Generation Chip(5V/3.3V ÷2 ，÷4/6時(shí)鐘發(fā)生芯片) |
| 中文描述： | 5V/3.3V ÷ 2，÷ 4 / 6時(shí)鐘發(fā)生器芯片（5V/3.3V ÷ 2，÷ 4 / 6時(shí)鐘發(fā)生芯片） |
| 文件頁數(shù)： | 1/4頁 |
| 文件大小： | 60K |
| 代理商： | SY10EL38L |
CLK
EN
MR
Function
Z
L
L
Divide
ZZ
H
L
Hold Q
0–3
X
X
H
Reset Q
0–3
Pin
Function
CLK
Differential Clock Inputs
EN
Synchronous Enable
MR
Master Reset
V
BB
Reference Output
Q
0,
Q
1
Differential
÷
2 Outputs
Differential
÷
4/6 Outputs
Q
2,
Q
3
DIVSEL
Frequency Select Input
The SY10/100EL38/L are low skew
÷
2,
÷
4/6 clock
generation chips designed explicitly for low skew clock
generation applications. The internal dividers are
synchronous to each other, therefore, the common output
edges are all precisely aligned. The devices can be driven
by either a differential or single-ended ECL or, if positive
power supplies are used, PECL input signal. In addition,
by using the V
BB
output, a sinusoidal source can be AC-
coupled into the device. If a single-ended input is to be
used, the V
BB
output should be connected to the CLK
input and bypassed to ground via a 0.01
μ
F capacitor.
The V
BB
output is designed to act as the switching
reference for the input of the EL38/L under single-ended
input conditions. As a result, this pin can only source/
sink up to 0.5mA of current.
The common enable (EN) is synchronous so that the
internal dividers will only be enabled/disabled when the
internal clock is already in the LOW state. This avoids
any chance of generating a runt clock pulse on the
internal clock when the device is enabled/disabled as
can happen with an asynchronous control. An internal
runt pulse could lead to losing synchronization between
the internal divider stages. The internal enable flip-flop is
clocked on the falling edge of the input clock, therefore,
all associated specification limits are referenced to the
negative edge of the clock input.
The Phase_Out output will go HIGH for one clock cycle
whenever the
÷
2 and the
÷
4/6 outputs are both
transitioning from a LOW to a HIGH. This output allows
for clock synchronization within the system.
Upon start-up, the internal flip-flops will attain a
random state; the master reset (MR) input allows for the
synchronization of the internal dividers, as well as for
multiple EL38/Ls in a system.
PIN CONFIGURATION/BLOCK DIAGRAM
I
3.3V and 5V power supply options
I
50ps output-to-output skew
I
Synchronous enable/disable
I
Master Reset for synchronization
I
Internal 75K
input pull-down resistors
I
Available in 20-pin SOIC package
TRUTH TABLE
PIN NAMES
DESCRIPTION
FEATURES
Rev.: E
Issue Date:
Amendment: /0
August, 1998
5V/3.3V
÷
2,
÷
4/6 CLOCK
GENERATION CHIP
NOTE:
Z = LOW-to-HIGH transition
ZZ = HIGH-to-LOW transition
DIVSEL
Q
2,
Q
3
OUTPUTS
0
Divide by 4
1
Divide by 6
ClockWorks
SY10EL38/L
SY100EL38/L
V
CC
Q
0
Q
0
Q
1
Q
1
Q
2
Q
2
Q
3
Q
3
V
EE
V
CC
EN
DIVSEL CLK
CLK
V
BB
MR
V
CC
P
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
P
TOP VIEW
SOIC
Z20-1
1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SY100EL38 | 5V/3.3V ÷2 ，÷4/6 Clock Generation Chip(5V/3.3V ÷2 ，÷4/6時(shí)鐘發(fā)生芯片) |
| SY100EL38L | 5V/3.3V ÷2 ，÷4/6 Clock Generation Chip(5V/3.3V ÷2 ，÷4/6時(shí)鐘發(fā)生芯片) |
| SY10EL51 | Differential Clock D Flip-Flop(差分時(shí)鐘D觸發(fā)器) |
| SY10EL57 | 4:1 Differential Multiplexer(差分4選1多路器) |
| SY10ELT21LZC | 3.3V DIFFERENTIAL LVPECL-to-LVTTL TRANSLATOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SY10EL38LZC | 功能描述:IC CLK GEN /2 /4/6 5/3.3V 20SOIC RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:10EL, Precision Edge® 標(biāo)準(zhǔn)包裝:27 系列:Precision Edge® 類型:頻率合成器 PLL:是 輸入:PECL，晶體 輸出:PECL 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/是 頻率 - 最大:800MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 5.25 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC 包裝:管件 |
| SY10EL38LZC TR | 功能描述:IC CLK GEN /2 /4/6 5/3.3V 20SOIC RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:10EL, Precision Edge® 標(biāo)準(zhǔn)包裝:27 系列:Precision Edge® 類型:頻率合成器 PLL:是 輸入:PECL，晶體 輸出:PECL 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/是 頻率 - 最大:800MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 5.25 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC 包裝:管件 |
| SY10EL38LZG | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 3.3V /2, /4-/6 Clock Generation Chip (I Temp, Green) RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SY10EL38LZG TR | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 3.3V /2, /4-/6 Clock Generation Chip (I Temp, Green) RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SY10EL38LZI | 功能描述:IC CLK GEN /2 /4/6 5/3.3V 20SOIC RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:10EL, Precision Edge® 標(biāo)準(zhǔn)包裝:27 系列:Precision Edge® 類型:頻率合成器 PLL:是 輸入:PECL，晶體 輸出:PECL 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/是 頻率 - 最大:800MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 5.25 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC 包裝:管件 |
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