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參數(shù)資料
| 型號(hào)： | SY100H603 |
| 廠商： | Micrel Semiconductor,Inc. |
| 英文描述： | 9-BIT LATCHED ECL-TO-TTL |
| 中文描述： | 9位鎖存ECL至TTL電 |
| 文件頁數(shù)： | 1/4頁 |
| 文件大?。?/td> | 71K |
| 代理商： | SY100H603 |
1
SY10H603
SY10H603
SY100H603
Micrel, Inc.
M9999-032906
hbwhelp@micrel.com or (408) 955-1690
Pin
Function
GND
TTL Ground (0V)
V
CCE
ECL V
CC
(0V)
V
CCT
TTL Supply (+5.0V)
V
EE
ECL Supply (–5.2/–4.5V)
D
0
–D
8
Data Inputs (ECL)
Q
0
–Q
8
Data Outputs (TTL)
OEECL
3-state Control (ECL)
LEN
Latch Enable (ECL)
MR
Master Reset (ECL)
DESCRIPTION
FEATURES
I
9-bit ideal for byte-parity applications
I
3-state TTL outputs
I
Flow-through configuration
I
Extra TTL and ECL power/ground pins to minimize
switching noise
I
Dual supply
I
6.0ns max. delay into 50pF, 12ns into 200pF (all
outputs switching)
I
PNP TTL inputs for low loading
I
Choice of ECL compatibility: MECL 10KH (10Hxxx)
or 100K (100Hxxx)
I
Fully compatible with MC10H/100H603
I
Available in 28-pin PLCC package
The SY10/100H603 are 9-bit, dual supply ECL-to-TTL
translators. Devices in the Micrel 9-bit translator series
utilize the 28-lead PLCC for optimal power pinning, signal
flow-through and electrical performance.
The devices feature a 48mA TTL output stage and AC
performance is specified into both a 50pF and 200pF
load capacitance. Latching is controlled by Latch Enable
(LEN) and Master Reset (MR) resets the latches. A HIGH
on OEECL sends the outputs into the high impedance
state. All control inputs are ECL level.
The 10H version is compatible with MECL 10KH ECL
logic levels. The 100H version is compatible with 100K
levels.
9-BIT LATCHED
ECL-TO-TTL
Rev.: E
Issue Date:
Amendment: /0
March 2006
BLOCK DIAGRAM
Q
0
D
0
ECL
LEN
MR
TTL
Q
D
EN
Q
1
D
1
Q
D
EN
Q
2
D
2
Q
D
EN
Q
3
D
3
Q
D
EN
Q
4
D
4
Q
D
EN
Q
5
D
5
Q
D
EN
Q
6
D
6
Q
D
EN
Q
7
D
7
Q
D
EN
Q
8
D
8
Q
D
EN
OEECL
PIN NAMES
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SY100H603JZ | 9-BIT LATCHED ECL-TO-TTL |
| SY100H603JZTR | 9-BIT LATCHED ECL-TO-TTL |
| SY10H603JZ | 9-BIT LATCHED ECL-TO-TTL |
| SY10H603JZTR | 9-BIT LATCHED ECL-TO-TTL |
| SY100H607 | REGISTERED HEX PECL-TO-TTL |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SY100H603JC | 功能描述:IC TRANSLATOR 9-BIT LATCH 28PLCC RoHS:否 類別:集成電路 (IC) >> 邏輯 - 變換器 系列:100H 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:100 系列:- 邏輯功能:變換器，雙向 位數(shù):2 輸入類型:CMOS 輸出類型:CMOS 數(shù)據(jù)速率:16Mbps 通道數(shù):2 輸出/通道數(shù)目:1 差分 - 輸入:輸出:無/無 傳輸延遲（最大）:15ns 電源電壓:1.65 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:10-UFQFN 供應(yīng)商設(shè)備封裝:10-UTQFN（1.4x1.8） 包裝:管件 |
| SY100H603JC TR | 功能描述:IC TRANSLATOR 9-BIT LATCH 28PLCC RoHS:否 類別:集成電路 (IC) >> 邏輯 - 變換器 系列:100H 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:100 系列:- 邏輯功能:變換器，雙向 位數(shù):2 輸入類型:CMOS 輸出類型:CMOS 數(shù)據(jù)速率:16Mbps 通道數(shù):2 輸出/通道數(shù)目:1 差分 - 輸入:輸出:無/無 傳輸延遲（最大）:15ns 電源電壓:1.65 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:10-UFQFN 供應(yīng)商設(shè)備封裝:10-UTQFN（1.4x1.8） 包裝:管件 |
| SY100H603JZ | 功能描述:轉(zhuǎn)換 - 電壓電平 9-bit Latched ECL-to-TTL (Lead Free) RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時(shí)間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
| SY100H603JZ TR | 功能描述:轉(zhuǎn)換 - 電壓電平 9-bit Latched ECL-to-TTL (Lead Free) RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時(shí)間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
| SY100H606JC | 功能描述:IC REGISTERED HEX 6-BIT 28-PLCC RoHS:否 類別:集成電路 (IC) >> 邏輯 - 變換器 系列:100H 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:100 系列:- 邏輯功能:變換器，雙向 位數(shù):2 輸入類型:CMOS 輸出類型:CMOS 數(shù)據(jù)速率:16Mbps 通道數(shù):2 輸出/通道數(shù)目:1 差分 - 輸入:輸出:無/無 傳輸延遲（最大）:15ns 電源電壓:1.65 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:10-UFQFN 供應(yīng)商設(shè)備封裝:10-UTQFN（1.4x1.8） 包裝:管件 |
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