參數(shù)資料
型號(hào): SY100H602JZ
廠商: MICREL INC
元件分類: 通用總線功能
英文描述: 9-BIT LATCHED TTL-TO-ECL
中文描述: 9 TTL TO ECL TRANSLATOR, TRUE OUTPUT, PQCC28
封裝: LEAD FREE, PLASTIC, LCC-28
文件頁(yè)數(shù): 1/4頁(yè)
文件大?。?/td> 70K
代理商: SY100H602JZ
1
SY10H602
SY10H602
SY100H602
Micrel, Inc.
M9999-032906
hbwhelp@micrel.com or (408) 955-1690
Pin
Function
GND
TTL Ground (0V)
V
CCE
ECL V
CC
(0V)
V
CCO
ECL V
CC
(0V) — Outputs
V
CCT
TTL Supply (+5.0V)
V
EE
ECL Supply (–5.2/–4.5V)
D
0
–D
8
Data Inputs (TTL)
Q
0
–Q
8
Data Outputs (ECL)
ENECL
Enable Control (ECL)
LEN
Latch Enable (ECL)
MR
Master Reset (ECL)
DESCRIPTION
FEATURES
I
9-bit ideal for byte-parity applications
I
Flow-through configuration
I
Extra TTL and ECL power/ground pins to minimize
switching noise
I
Dual supply
I
3.5ns max. D to Q
I
PNP TTL inputs for low loading
I
Choice of ECL compatibility: MECL 10KH (10Hxxx)
or 100K (100Hxxx)
I
Fully compatible with MC10H/100H602
I
Available in 28-pin PLCC package
The SY10/100H602 are 9-bit, dual supply TTL-to-ECL
translators with latches. Devices in the Micrel 9-bit
translator series utilize the 28-lead PLCC for optimal
power pinning, signal flow-through and electrical
performance.
The H602 features D-type latches. Latching is
controlled by Latch Enable (LEN), while the Master Reset
input resets the latches. A post-latch logic enable is also
provided (ENECL), allowing control of the output state
without destroying latch data. All control inputs are ECL
level.
The 10H version is compatible with MECL 10KH ECL
logic levels. The 100H version is compatible with 100K
levels.
9-BIT LATCHED
TTL-TO-ECL
Rev.: E
Issue Date:
Amendment: /0
March 2006
BLOCK DIAGRAM
Q
0
D
0
TTL
LEN
MR
ECL
Q
D
EN
Q
1
D
1
Q
D
EN
Q
2
D
2
Q
D
EN
Q
3
D
3
Q
D
EN
Q
4
D
4
Q
D
EN
Q
5
D
5
Q
D
EN
Q
6
D
6
Q
D
EN
Q
7
D
7
Q
D
EN
Q
8
D
8
Q
D
EN
ENECL
PIN NAMES
相關(guān)PDF資料
PDF描述
SY100H602JZTR 9-BIT LATCHED TTL-TO-ECL
SY10H602JZ 9-BIT LATCHED TTL-TO-ECL
SY10H602JZTR 9-BIT LATCHED TTL-TO-ECL
SY100H606JZ REGISTERED HEX TTL-TO-PECL
SY100H606JZTR REGISTERED HEX TTL-TO-PECL
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