參數(shù)資料
型號: SY100EPT21LKCTR
廠商: MICREL INC
元件分類: 通用總線功能
英文描述: 3.3V DIFFERENTIAL LVPECL-to-LVTTL TRANSLATOR
中文描述: PECL TO TTL TRANSLATOR, TRUE OUTPUT, PDSO8
封裝: MSOP-8
文件頁數(shù): 1/8頁
文件大小: 87K
代理商: SY100EPT21LKCTR
Pin
Function
Q
LVTTL Output
D, /D
Differential LVPECL Input Pair
V
CC
V
BB
GND
Positive Supply
Output Reference Voltage
Ground
DESCRIPTION
I
3.3V power supply
I
1.9ns typical propagation delay
I
275MHz f
MAX
(Clock bit stream, not pseudo-random)
I
Differential LVPECL inputs
I
24mA LVTTL outputs
I
Flow-through pinouts
I
Internal input resistors: pulldown on D, pulldown
and pullup on /D
I
Q output will default LOW with inputs open or at
GND
I
V
BB
output
I
Available in 8-pin MSOP and SOIC package
The SY100EPT21L is a single differential LVPECL-to-
LVTTL translator using a single +3.3V power supply.
Because LVPECL (Low Voltage Positive ECL) levels are
used, only +3.3V and ground are required. The small
outline 8-lead SOIC package and low skew single gate
design make the EPT21L ideal for applications that
require the translation of a clock or data signal where
minimal space, low power, and low cost are critical.
V
BB
allows a differential, single-ended, or AC-coupled
interface to the device. If used, the V
BB
output should be
bypassed to V
CC
with 0.01
μ
F capacitor.
Under open input conditions, the /D will be biased at a
V
CC
/2 voltage level and the D input will be pulled to
ground. This condition will force the Q output low to
provide added stability.
The 100EPT is compatible with positive ECL 100K
logic levels.
FEATURES
3.3V DIFFERENTIAL
LVPECL-to-LVTTL
TRANSLATOR
PIN NAMES
PIN CONFIGURATION/BLOCK DIAGRAM
(Available in 8-pin SOIC and 8-pin MSOP)
SY100EPT21L
1
NC
D
D
V
BB
8
V
CC
Q
NC
GND
7
6
5
2
3
4
LVPECL
LVTTL
1
Rev.: A
Issue Date:
Amendment: /1
July 2000
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