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參數(shù)資料
| 型號： | SY100EP196VTI |
| 廠商： | MICREL INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | 3.3V/5V 2.5GHz PROGRAMMABLE DELAY WITH FINE TUNE CONTROL |
| 中文描述： | ACTIVE DELAY LINE, COMPLEMENTARY OUTPUT, PQFP32 |
| 封裝： | TQFP-32 |
| 文件頁數(shù)： | 3/18頁 |
| 文件大小： | 628K |
| 代理商： | SY100EP196VTI |
3
ECL Pro
SY100EP196V
Micrel, Inc.
M9999-120505
hbwhelp@micrel.com or (408) 955-1690
Pin Number
23, 25, 26, 27, 29,
30, 31, 32, 1, 2
Pin Name
D[0:9]
Pin Function
CMOS, ECL, or TTL Select Inputs: These digital control signals adjust the amount of
delay from IN to Q. Please refer to the “AC Electrical Table” (page 3) and Table 7 (page
17) for delay values. Figure 9 shows how to interface these inputs to various logic family
standards. These inputs default to logic low when left unconnected. Bit 0 is the least
significant bit, and bit 9 is the most significant bit.
CMOS, ECL, or TTL Select Input: This input latches just like D[0:9] does. It drives the
CASCADE, /CASCADE differential pair. Use only when cascading two or more
SY100EP196V to extend the range of delays required.
ECL Input: This is the signal to be delayed. If this input pair is left unconnected, this is
equivalent to a logic low input.
Voltage Output Reference: When using a single-ended logic source for IN and /IN,
connect the unused input of the differential pair to this pin. This pin can also re-bias AC-
coupled inputs to IN and /IN. When used, de-couple this pin to V
CC
through an 0.01
μ
F
capacitor. Limit current sinking or sourcing to 0.5mA or less.
Voltage Output: Connect this pin to VCF when the D inputs are ECL. Refer to the
“Digital
Control Logic Standard”
section of the
“Functional Description”
to interface the D inputs to
CMOS or TTL.
Voltage Input: The voltage at this pin sets the logic transition threshold for the D inputs.
Most Negative Supply. Supply ground for PECL systems.
ECL Control Input: When logic low, the D inputs flow through. Any changes to the D inputs
reflect in the delay between IN, /IN and Q, /Q. When logic high, the logic values at D are
latched, and these latched bits determine the delay.
ECL Control Input: When logic high, the contents of the D register are reset. This sets the
delay to the minimum possible, equivalent to D[0:9] being set to 0000000000. When logic
low, the value of the D register, or the logic value of SETMAX determines the delay from
IN, /IN to Q, /Q. This input defaults to logic low when left unconnected.
ECL Control Input: When logic high and SETMIN is logic low, the contents of the D
register are set high, and the delay is set to one step greater than the maximum possible
with D[0:9] set to 1111111111. When logic low, the value of the D register, or the logic
value of SETMIN determines the delay from IN, /IN to Q, /Q. This input defaults to logic
low when left unconnected.
Most Positive Supply: Supply ground for NECL systems. Bypass to V
EE
with 0.1
μ
F and
0.01
μ
F low ESR capacitors.
100k ECL Outputs: These outputs are used when cascading two or more SY100EP196V
to /CASCADE extend the delay range required. Refer to Table 7 (page 17) for delay
values.
ECL Control Input: When set active low, Q, /Q are a delayed version of IN, /IN. When set
inactive high, IN, /IN are gated such that Q, /Q become a differential logic low. This input
defaults to logic low when left unconnected.
Voltage Control Input: By varying the voltage at this pin from V
CC
through V
EE
, the delay
may be fine tuned by approximately
±
15ps.
100k ECL Outputs: This signal pair is the delayed version of IN, /IN.
3
D[10]
4, 5
IN, /IN
6
VBB
7
VEF
8
VCF
VEE
LEN
9, 24, 28
10
11
SETMIN
12
SETMAX
13, 18, 19, 22
VCC
14, 15
CASCADE,
16
/EN
17
FTUNE
20, 21
Q, /Q
PIN DESCRIPTION
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| SY100EP196VTI TR | 功能描述:IC DELAY LINE 1024TAP 32-TQFP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 延遲線 系列:100EP, ECL Pro® 標準包裝:2,500 系列:- 標片/步級數(shù):- 功能:多個，不可編程 延遲到第一抽頭:10ns 接頭增量:- 可用的總延遲:10ns 獨立延遲數(shù):4 電源電壓:4.75 V ~ 5.25 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:14-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:14-SOIC 包裝:帶卷 (TR) |
| SY100EP210UTG | 功能描述:緩沖器和線路驅(qū)動器 2.5-5V Dual 1:5 PECL Fanout Buffer (I Temp, Green) RoHS:否 制造商:Micrel 輸入線路數(shù)量:1 輸出線路數(shù)量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel |
| SY100EP210UTG TR | 功能描述:緩沖器和線路驅(qū)動器 2.5-5V Dual 1:5 PECL Fanout Buffer (I Temp, Green) RoHS:否 制造商:Micrel 輸入線路數(shù)量:1 輸出線路數(shù)量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel |
| SY100EP210UTI | 功能描述:IC CLOCK BUFFER 1:5 3GHZ 32-TQFP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘緩沖器，驅(qū)動器 系列:100EP, Precision Edge® 標準包裝:1 系列:HiPerClockS™ 類型:扇出緩沖器（分配），多路復(fù)用器 電路數(shù):1 比率 - 輸入:輸出:2:18 差分 - 輸入:輸出:是/無 輸入:CML，LVCMOS，LVPECL，LVTTL，SSTL 輸出:LVCMOS，LVTTL 頻率 - 最大:250MHz 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:- 其它名稱:800-1923-6 |
| SY100EP210UTI TR | 功能描述:IC CLOCK BUFFER 1:5 3GHZ 32-TQFP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘緩沖器，驅(qū)動器 系列:100EP, Precision Edge® 標準包裝:1 系列:HiPerClockS™ 類型:扇出緩沖器（分配），多路復(fù)用器 電路數(shù):1 比率 - 輸入:輸出:2:18 差分 - 輸入:輸出:是/無 輸入:CML，LVCMOS，LVPECL，LVTTL，SSTL 輸出:LVCMOS，LVTTL 頻率 - 最大:250MHz 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:- 其它名稱:800-1923-6 |
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