參數(shù)資料
型號： SY100EP196VTG
廠商： MICREL INC
元件分類： 通用總線功能
英文描述： 3.3V/5V 2.5GHz PROGRAMMABLE DELAY WITH FINE TUNE CONTROL
中文描述： ACTIVE DELAY LINE, COMPLEMENTARY OUTPUT, PQFP32
封裝： LEAD FREE, TQFP-32
文件頁數(shù)： 7/18頁
文件大小： 628K
代理商： SY100EP196VTG
7
ECL Pro
SY100EP196V
Micrel, Inc.
M9999-120505
hbwhelp@micrel.com or (408) 955-1690
AC ELECTRICAL CHARACTERISTICS
V
CC
= 3.0 to 5.5V, V
EE
= 0V or V
CC
= 0V, V
EE
= –3.0 to –5.5V; T
A
= –40
°
C to +85
°
C
(12, 13)
T
A
= –40
°
C
Typ
2.5
T
A
= +25
°
C
Typ
2.5
T
A
= +85
°
C
Typ
2.5
Symbol
f
MAX
t
PD
Parameter
Min
Max
Min
Max
Min
Max
Unit
GHz
Maximum Frequency
(14)
Propagation Delay
IN to Q; D[0-10]=0
IN to Q; D[0-10]=1023
/EN to Q: D[0-10]=0
D10 to CASCADE
Programmable Range
t
PD
(max)-t
PD
(min)
Step Delay
(15)
1650
9500
1600
300
2000
11500
2150
420
2450
13500
2600
500
1800
9800
1800
325
2050
12200
2300
450
2600
14000
2800
550
1950
10600
2000
325
2250
13300
2500
525
2750
15800
3000
625
ps
ps
ps
ps
t
RANGE
7850
9450
8200
10000
8850
10950
ps
t
D0 High
D1 High
D2 High
D3 High
D4 High
D5 High
D6 High
D7 High
D8 High
D9 High
9
25
42
75
142
296
532
1080
2100
4250
±
10
10
26
42
80
143
300
540
1095
2150
4300
±
10
10
27
43
81
150
310
565
1140
2250
4500
±
10
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
Lin
t
SKEW
Linearity
(16)
Duty Cycle Skew
(17)
%LSB
t
PHL
-t
PLH
D to LEN
D to IN
(18)
/EN to IN
(19)
LEN to D
IN to /EN
(20)
25
0
160
170
100
280
ps
ps
ps
ps
ps
ps
t
S
Setup Time
200
300
300
200
400
0
200
300
300
200
400
200
300
300
200
400
0
140
150
60
250
180
180
80
300
t
H
Hold Time
t
R
Release Time
/EN to IN
(21)
SETMAX to LEN
SETMIN to LEN
500
250
200
0.2
800
ps
ps
ps
400
350
200
275
0.2
800
400
350
400
350
300
335
0.2
800
t
JIT
V
PP
t
r
t
f
Cycle-to-Cycle Jitter
(22)
Input Voltage Swing (Differential)
Output Rise/Fall Time
20% to 80% (Q)
20% to 80% (CASCADE)
< 1
1200
< 1
1200
< 1
1200
ps
RMS
mV
150
150
150
180
180
250
250
210
210
300
300
230
230
325
325
ps
ps
Notes:
12. AC characteristics are guaranteed by design and characterization.
13. Measured using 750mV source, 50% duty cycle clock source.
14. Refer to
“Typical Operating Characteristics”
for output swing performance.
15. The delays of the individual bits are cumulative.
16. Linearity is the deviation from the ideal delay.
17. Duty cycle skew guaranteed only for differential operation measured from the crosspoint of the input edge to the crosspoint of the corresponding
output edge.
18. Setup time defines the amount of time prior to an edge on IN, /IN that the D[0:9] bits must be set to guarantee the new delay will occur for that edge.
19. Setup time is the minimum that /EN must be asserted prior to the next transition of IN, /IN to prevent an output response greater than
±
75mV to that
IN, /IN transition.
20. Hold time is the minimum time that /EN must remain asserted after a negative going IN or a positive going /IN to prevent an output response greater
than
±
75mV to that IN, /IN transition.
21. Release time is the minimum time that /EN must be deasserted prior to the next IN, /IN transition to ensure an output response that meets the
specified IN to Q propagation delay and transition times.
22. This is the amount of generated jitter added to an otherwise jitter free clock signal, going from IN, /IN to Q, /Q, where the clock may be any frequency
between 0.0 and 2.5GHz.
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