參數(shù)資料
型號: SY100EL52ZCTR
廠商: MICREL INC
元件分類: 通用總線功能
英文描述: DIFFERENTIAL DATA AND CLOCK D FLIP-FLOP
中文描述: 100EL SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO8
封裝: 0.150 INCH, SOIC-8
文件頁數(shù): 1/4頁
文件大小: 49K
代理商: SY100EL52ZCTR
DESCRIPTION
I
365ps propagation delay
I
2.0GHz toggle frequency
I
Internal 75K
input pull-down resistors
I
Available in 8-pin SOIC package
The SY10/100EL52 are differential data, differential
clock D flip-flops. These devices are functionally
equivalent to the E452 devices, with higher performance
capabilities. With propagation delays and output transition
times significantly faster than the E452, the EL52 is ideally
suited for those applications which require the ultimate
in AC performance.
Data enters the master portion of the flip-flop when
the clock is LOW and is transferred to the slave, and
thus the outputs, upon a positive transition of the clock.
The differential clock inputs also allow the EL52 to be
used as a negative edge triggered device.
The EL52 employs input clamping circuitry so that,
under open input conditions (pulled down to V
EE
), the
outputs of the device will remain stable.
FEATURES
DIFFERENTIAL DATA AND
CLOCK D FLIP-FLOP
PIN CONFIGURATION/BLOCK DIAGRAM
D
CLK
Q
L
Z
L
H
Z
H
NOTE:
1. Z = LOW-to-HIGH transition.
SOIC
TOP VIEW
Pin
Function
D
Data Input
CLK
Clock Input
Q
Data Output
1
2
3
4
5
6
7
8
D
V
CC
Q
V
EE
Q
CLK
Flip-Flop
D
CLK
D
Rev.: F
Issue Date:
Amendment: /0
August, 1998
SY10EL52
SY100EL52
TRUTH TABLE
(1)
PIN NAMES
1
相關(guān)PDF資料
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SY100EL52ZGTR 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:DIFFERENTIAL DATA AND CLOCK D FLIP-FLOP
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