hbwhelp@micrel.com or (408) 955-1690
參數(shù)資料
型號: SY100EL17VZG
廠商: Micrel Inc
文件頁數(shù): 5/5頁
文件大?。?/td> 0K
描述: IC RECEIVER QUAD DIFF 20-SOIC
標準包裝: 38
系列: 100EL
邏輯類型: 差分接收器
電源電壓: 3.3V,5V
位數(shù): 8
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-SOIC(0.295",7.50mm 寬)
供應商設備封裝: 20-SOIC(寬型)
包裝: 管件
產(chǎn)品目錄頁面: 1087 (CN2011-ZH PDF)
其它名稱: 576-3388-5
SY100EL17VZG-ND
Micrel, Inc.
SY89218U
August 2007
5
M9999-082407-C
hbwhelp@micrel.com or (408) 955-1690
Pin Description (continued)
Pin Number
Pin Name
Pin Function
64
EN
Single-Ended Input: This TTL/CMOS input disables and enables the outputs. It is
internally connected to a 25k
pull-up resistor and will default to logic HIGH state if left
open. When disabled, true outputs go LOW and complementary outputs switch to HIGH.
The input switching threshold is VCC/2. For the input enable and disable functional
description, refer to Figures 2d and 2e.
19, 32, 49, 63
GND,
Exposed Pad
Ground and exposed pad must be connected to the same GND plane on the board.
Function Table
/MR
(1)
EN
(2, 3)
CLK_SEL
FSELx0
(4)
FSELx1
(4)
Q
1
0
IN0÷1
1
0
IN1÷1
1
0
1
0
IN0÷2
1
0
IN1÷2
1
0
X
1
IN0÷4
1
X
1
IN1÷4
1
0
X
0
X
0
Notes:
1.
/MR asynchronously forces Q to LOW (/Q to HIGH).
2.
EN forces Q LOW between 2 and 6 input clock cycles after the falling edge of EN. Refer to “Timing Diagram” section.
3.
EN synchronously enables Q between two and six input clock cycles after the rising edge of EN. Refer to “Timing Diagram” section.
4.
FSEL valid for each of the banks A, B, C, and D. Banks can be programmed independent of each other.
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