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Pin
Function
SINA, SINA
Differential Serial Data Input A
SINB, SINB
Differential Serial Data Input B
SEL
Serial Input Select Pin
SOUT, SOUT
Differential Serial Data Output
Q0–Q3
Parallel Data Outputs
CLK, CLK
Differential Clock Inputs
CL/4, CL/4
Differential
÷
4 Clock Output
Differential
÷
8 Clock Output
Conversion Mode 4-bit/8-bit
CL/8, CL/8
MODE
SYNC
Conversion Synchronizing Input
RESET
Input, Resets the Counters
V
CCO
V
CC
to Output
DESCRIPTION
FEATURES
I
On-chip clock
÷
4 and
÷
8
I
Extended 100E V
EE
range of –4.2V to –5.5V
I
2.5Gb/s data rate capability
I
Differential clock and serial inputs
I
V
BB
output for single-ended use
I
Asynchronous data synchronization
I
Mode select to expand to 8 bits
I
Internal 75k
input pull-down resistors
I
Fully compatible with Motorola MC10E/100E445
I
Available in 28-pin PLCC package
4-BIT SERIAL-to-PARALLEL
CONVERTER
The SY10/100E445 are integrated 4-bit serial-to-parallel
data converters. The devices are designed to operate for
NRZ data rates of up to 2.5Gb/s. The chip generates a
divide-by-4 and a divide-by-8 clock for both 4-bit conversion
and a two-chip 8-bit conversion function. The conversion
sequence was chosen to convert the first serial bit to Q
0
,
the second to Q
1
, etc.
Two selectable serial inputs provide a loopback capability
for testing purposes when the device is used in conjunction
with the E446 parallel-to-serial converter.
The start bit for conversion can be moved using the
SYNC input. A single pulse, applied asynchronously for at
least two input clock cycles, shifts the start bit for conversion
from Q
n
to Q
n-1
by one bit. For each additional shift required,
an additional pulse must be applied to the SYNC input.
Asserting the SYNC input will force the internal clock dividers
to "swallow" a clock pulse, effectively shifting a bit from the
Q
n
to the Q
n-1
output (see Timing Diagram B).
The MODE input is used to select the conversion mode
of the device. With the MODE input LOW (or open) the
device will function as a 4-bit converter. When the mode
input is driven HIGH, the data on the output will change on
every eighth clock cycle, thus allowing for an 8-bit conversion
scheme using two E445s. When cascaded in an 8-bit
conversion scheme, the devices will not operate at the
2.5Gb/s data rate of a single device. Refer to the applications
section of this data sheet for more information on cascading
the E445.
For lower data rate applications, a V
BB
reference voltage
is supplied for single-ended inputs. When operating at clock
rates above 500MHz, differential input signals are
recommended. For single-ended inputs, the V
BB
pin is tied
to the inverting differential input and bypassed via a 0.01
μ
F
capacitor. The V
BB
provides the switching reference for the
input differential amplifier. The V
BB
can also be used to AC
couple an input signal.
SY10E445
SY100E445
Rev.: D
Issue Date:
Amendment: /0
October, 1998
PIN CONFIGURATION
PIN NAMES
18
17
16
15
14
13
12
5
6
7
8
9
10 11
26
27
28
1
2
3
4
TOP VIEW
PLCC
J28-1
25 24 23 22 21 20 19
S
INB
S
INB
SEL
V
EE
CLK
CLK
V
BB
C
V
C
C
V
C
Q
3
C
C
S
OUT
S
OUT
V
CC
Q
0
Q
1
V
CCO
Q
2
S
R
M
N
S
I
V
C
S
I
1