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參數(shù)資料
| 型號(hào)： | SY100E336JC |
| 廠商： | MICREL INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | RECTIFIER STANDARD SINGLE 3A 800V 800 125A-ifsm 5uA-ir 1.1V-vf DO-201AD 1.2K/REEL-13 |
| 中文描述： | 100E SERIES, 3-BIT REGISTERED TRANSCEIVER, INVERTED OUTPUT, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁(yè)數(shù)： | 1/4頁(yè) |
| 文件大?。?/td> | 64K |
| 代理商： | SY100E336JC |
FEATURES
I
25
cutoff bus output
I
Extended 100E V
EE
range of –4.2V to –5.5V
I
50
receiver output
I
Transmit and receive registers
I
1500ps max. clock to bus
I
1000ps max. clock to Q
I
Internal edge slow-down capacitors on bus outputs
I
Additional package ground pins
I
Fully compatible with industry standard 10KH,
100K ECL levels
I
Internal 75K
input pulldown resistors
I
Fully compatible with Motorola MC10E/100E336
I
Available in 28-pin PLCC package
DESCRIPTION
The SY10/100E336 offer three bus transceivers with
both transmit and receive registers and are designed for
use in new, high-performance ECL systems. The bus
outputs (BUS
0
- BUS
2
) are designed to drive a 25
bus.
The receive outputs (Q
0
– Q
2
) are specified for 50
. The
bus outputs feature a normal logic HIGH level (V
OH
) and a
cutoff LOW level when at a logic LOW. At cutoff, the outputs
go to –2.0V and the output emitter-follower is “off”,
presenting a high impedance to the bus. The bus outputs
have edge slow-down capacitors.
The Transmit Enable pins (TEN) determine whether
current data is held in the transmit register or new data is
loaded from the A/B inputs. A logic LOW on both of the bus
enable inputs (BUSEN), when clocked through the register,
disables the bus outputs to –2.0V.
The receiver section clocks bus data into the receive
registers after gating with the Receive Enable (RXEN)
input.
All registers are clocked by rising edge of CLK
1
or CLK
2
(or both).
Additional grounding is provided through the ground
pins (GND) which should be connected to 0V. The GND
pins are not electrically connected to the chip.
3-BIT REGISTERED
BUS TRANSCEIVER
PIN CONFIGURATION
Pin
Function
A
0
–A
2
Data Inputs A
B
0
–B
2
Data Inputs B
TEN
1, 2
Transmit Enable Inputs
RXEN
Receive Enable Input
BUSEN
1, 2
Bus Enable Inputs
CLK
1, 2
Clock Inputs
BUS
0
–BUS
2
25
Cutoff Bus Outputs
Q
0
–Q
2
Receive Data Outputs
V
CCO
V
CC
to Output
PIN NAMES
SY10E336
SY100E336
Rev.: C
Issue Date: February, 1998
Amendment: /2
TOP VIEW
PLCC
J28-1
26
27
28
1
2
3
4
18
17
16
15
14
13
12
25 24 23 22 21 20 19
5
6
7
8
9
10 11
V
C
A
2
B
2
T
1
T
2
N
Q
2
V
CC
Q
1
V
CCO
BUS
1
GND
BUS
2
GND
B
1
V
C
Q
0
A
1
B
0
G
B
0
V
EE
CLK
1
A
0
CLK
2
BUSEN
1
BUSEN
2
RXEN
1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SY10E336JCTR | RECTIFIER STANDARD SINGLE 3A 1000V 1000 125A-ifsm 5uA-ir 1.1V-vf DO-201AD 1.2K/REEL-13 |
| SY100E336JCTR | RECTIFIER STANDARD SINGLE 3A 1000V 1000 125A-ifsm 5uA-ir 1.1V-vf DO-201AD 500/BULK |
| SY10E336 | 3-BIT REGISTERED BUS TRANSCEIVER |
| SY100E336 | 3-Bit Registered Bus Transceiver(3位寄存總線收發(fā)器) |
| SY10E337JC | 3-BIT SCANNABLE |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SY100E336JCTR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3-BIT REGISTERED BUS TRANSCEIVER |
| SY100E336JZ | 功能描述:寄存器 3-bit Registered Bus Transceiver (Lead Free) RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| SY100E336JZ TR | 功能描述:寄存器 3-bit Registered Bus Transceiver (Lead Free) RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| SY100E336JZTR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3-BIT REGISTERED BUS TRANSCEIVER |
| SY100E337 | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3-BIT SCANNABLE REGISTERED BUS TRANSCEIVER |
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