參數(shù)資料
型號: SY100E111AJC
廠商: MICREL INC
元件分類: 時鐘及定時
英文描述: 5V/3.3V 1:9 DIFFERENTIAL CLOCK DRIVER w/o ENABLE
中文描述: 100E SERIES, LOW SKEW CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC28
封裝: PLASTIC, LCC-28
文件頁數(shù): 5/6頁
文件大?。?/td> 73K
代理商: SY100E111AJC
5
Precison Edge
SY10E111A/L
SY100E111A/L
Micrel, Inc.
M9999-032006
hbwhelp@micrel.com or (408) 955-1690
VEE = VEE (Min.) to VEE (Max.); VCC = GND
TA = -40
°CTA = 0°CTA = +25°CTA = +85°C
Symbol
Parameter
Min.
Typ. Max.
Min.
Typ. Max. Min.
Typ. Max. Unit
t
PD
Propagation Delay to Output
ps
IN (differential), Note 2
380
680
430
630
430
630
430
630
IN (single-ended), Note 3
280
780
330
730
330
730
330
730
t
skew
Within-Device Skew, Note 4
——
75
——
50
——
50
——
50
ps
Part-to-Part Skew (Diff.)
——
250
——
200
——
200
——
200
V
PP
Minimum Input Swing, Note 5
250
——
250
——
250
——
250
——
mV
V
CMR
Common Mode Range, Note 6
–1.5
—–0.4
–1.5
—–0.4
–1.5
—–0.4
–1.5
—–0.4
V
tr
Rise/Fall Times
200
650
200
600
200
600
200
600
ps
tf
20% to 80%
AC ELECTRICAL CHARACTERISTICS(1)
Note 1.
Parametric values specified at:
5 volt Power Supply Range
100E111A Series:
-4.2V to -5.5V.
10E111A Series
-4.75V to -5.5V.
3 volt Power Supply Range
10/100E111L Series:
-3.0V to -3.8V.
Note 2.
The differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing point of the
differential output signals.
Note 3.
The single-ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of the output signal.
Note 4.
The within-device skew is defined as the worst case difference between any two similar delay paths within a single device.
Note 5.
V
PP (min) is defined as the minimum input differential voltage which will cause no increase in the propagation delay. The VPP (min) is AC
limited for the E111A/L as a differential input as low as 50mV will still produce full ECL levels at the output.
Note 6.
V
CMR is defined as the range within the VIH level may vary, with the device still meeting the propagation delay specification. The VIL level
must be such that the peak-to-peak voltage is less than 1.0V and greater than or equal to V
PP (min).
For PECL operation: V
CMR (max) = VCC – |VCMR (max)| and VCMR (min) = VCC – |VCMR (min)|
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