參數(shù)資料
型號： STR912FW44X6T
廠商： 意法半導體
元件分類： ADC
英文描述： ARM966E-S 16/32-Bit Flash MCU with Ethernet, USB, CAN, AC Motor Control, 4 Timers, ADC, RTC, DMA
中文描述： ARM966E - ? 16/32位閃存微控制器與以太網，USB，加拿大，交流電機控制，4個計時器，模數(shù)轉換器，RTC和DMA的
文件頁數(shù)： 5/72頁
文件大?。?/td> 664K
代理商： STR912FW44X6T
STR91xF
Functional overview
13/72
See Table 1 for recommended interrupt source assignments to physical IRQ interrupt channels.
Interrupt source assignments are made by CPU firmware during initialization, thus establishing
interrupt priorities.
Table 1.
Recommended IRQ Channel assignments (set by CPU firmware)
VIC IRQ Channel
Logic Block
Interrupt Source
0 (high priority)
WatchDog
Timeout in WDT mode, Terminal Count in Counter Mode
1
CPU Firmware
Firmware generated interrupt
2
CPU Core
Debug Receive Command
3
CPU Core
Debug Transmit Command
4
TIM Timer 0
Logic OR of ICI0_0, ICI0_1, OCI0_0, OCI0_1, Timer overflow
5
TIM Timer 1
Logic OR of ICI1_0, ICI1_1, OCI1_0, OCI1_1, Timer overflow
6
TIM Timer 2
Logic OR of ICI2_0, ICI2_1, OCI2_0, OCI2_1, Timer overflow
7
TIM Timer 3
Logic OR of ICI3_0, ICI3_1, OCI3_0, OCI3_1, Timer overflow
8
USB
Logic OR of high priority USB interrupts
9
USB
Logic OR of low priority USB interrupts
10
CCU
Logic OR of all interrupts from Clock Control Unit
11
Ethernet MAC
Logic OR of Ethernet MAC interrupts via its own dedicated
DMA channel.
12
DMA
Logic OR of interrupts from each of the 8 individual DMA
channels
13
CAN
Logic OR of all CAN interface interrupt sources
14
IMC
Logic OR of 8 Induction Motor Control Unit interrupts
15
ADC
End of AtoD conversion interrupt
16
UART0
Logic OR of 5 interrupts from UART channel 0
17
UART1
Logic OR of 5 interrupts from UART channel 1
18
UART2
Logic OR of 5 interrupts from UART channel 2
19
I2C0
Logic OR of transmit, receive, and error interrupts of I2C
channel 0
20
I2C1
Logic OR of transmit, receive, and error interrupts of I2C
channel 1
21
SSP0
Logic OR of all interrupts from SSP channel 0
22
SSP1
Logic OR of all interrupts from SSP channel 1
23
BROWNOUT
LVD warning interrupt
24
RTC
Logic OR of Alarm, Tamper, or Periodic Timer interrupts
25
Wake-Up (all)
Logic OR of all 32 inputs of Wake-Up unit (30 pins, RTC, and
USB Resume)
26
Wake-up Group 0
Logic OR of 8 interrupt sources: RTC, USB Resume, pins
P3.2 to P3.7
27
Wake-up Group 1
Logic OR of 8 interrupts from pins P5.0 to P5.7
28
Wake-up Group 2
Logic OR of 8 interrupts from pins P6.0 to P6.7
29
Wake-up Group 3
Logic OR of 8 interrupts from pins P7.0 to P7.7
30
USB
USB Bus Resume Wake-up (also input to wake-up unit)
31 (low priority)
PFQ-BC
Special use of interrupts from Prefetch Queue and Branch
Cache
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