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參數(shù)資料
| 型號： | STR84145 |
| 廠商： | Allegro MicroSystems, Inc. |
| 英文描述： | LATCHED, UNIVERSAL INPUT-VOLTAGE SWITCHES |
| 中文描述： | 鎖存，通用輸入電壓開關(guān) |
| 文件頁數(shù)： | 3/8頁 |
| 文件大小： | 85K |
| 代理商： | STR84145 |
SIMPLIFIED OPERATION
ELECTRICAL CHARACTERISTICS
at T
A
= +25
°
C, voltage measurements are referenced to Common (pin 3)
(unless otherwise noted).
Limits
Characteristic
On-State Voltage
Symbol
V
TM
Test Conditions
STR83145, I
T
= 10 A*
STR84145, I
T
= 12 A*
STR83145, V
D
= 500 V
STR84145, V
D
= 500 V
V
T
= 2 V
C
2
= 1
μ
F, V
MT1
≥
100 V dc
V
DELAY
≤
1 V
Min.
–
Typ. Max.
–
Units
V
1.8
–
1.6
–
V
Off-State Current
I
DRM
–
–
100
μ
A
μ
A
–
40
–
Starting Voltage
V
S
t
D
V
C
–
–
100
V
Startup Time Delay
40
–
100
ms
DC Switch-Over Voltage
200
205
210
V
Temperature Coefficient
of Switch-Over Voltage
α
VC
I
MT1
-20
°
C
≤
T
M
≤
+100
°
C
Voltage-doubler mode, V
MT1
= 195 V
Full-bridge mode, V
MT1
= 400 V
–
±
45
–
mV/
°
C
Input Current
–
–
10
mA
–
–
6.5
mA
Delay Terminal Voltage
V
DELAY
f
o
V
R
R
θ
JM
–
–
7.0
V
Triac Gate-Drive Osc. Freq.
V
gate
ref. MT1, V
MT1
= 100 V
V
GATE
= 400 mV
FET channel to mounting surface
–
15
–
kHz
Latch Reset Voltage
2.0
–
15
V
Thermal Resistance
–
–
1.8
°
C/W
NOTES: Negative current is defined as coming out of (sourcing) the specified device terminal.
Typical Data is for design information only.
*In practical use, I
T
is recommended derated to 70%.
+
+
8
240–373 V peak
+
+
1
246–373 V peak
Full-Bridge Mode
Dwg. EK-006
Voltage-Doubler Mode
STR83145
AND
STR84145
LATCHED, UNIVERSAL
INPUT-VOLTAGE SWITCHES
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