參數(shù)資料
型號(hào): STR751FR0
廠商: 意法半導(dǎo)體
元件分類: ADC
英文描述: Zener Diode; Application: General; Pd (mW): 400; Vz (V): 29.02 to 30.51; Condition Iz at Vz (mA): 5; C (pF) max: -; Condition VR at C (V):   ESD (kV) min: -; Package: MHD
中文描述: 的ARM7TDMI - S⑩32位微控制器的閃存,新措施,3性病16位定時(shí)器,PWM定時(shí)器,快速的10位ADC和I2C,UART的,過(guò)磷酸鈣,USB和CAN
文件頁(yè)數(shù): 29/84頁(yè)
文件大小: 997K
代理商: STR751FR0
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Electrical parameters
35/84
5.3.2
Operating conditions at power-up / power-down
Subject to general operating conditions for TA.
5.3.3
Embedded voltage regulators
Subject to general operating conditions for VDD_IO, and TA
Table 11.
Operating conditions at power-up / power-down
Symbol
Parameter
Conditions
Min(1)
1.
Data guaranteed by characterization, not tested in production.
Typ
Max(1)
Unit
tVDD_IO
VDD_IO rise time rate
20
s/V
20
ms/V
tV18
V18 rise time rate
(1)
When 1.8 V power is supplied
externally
20
s/V
20
ms/V
Table 12.
Embedded voltage regulators
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VMVREG
MVREG power supply(1)
1.
VMVREG is observed on the V18, V18REG and V18BKP pins except in the following case:
- In STOP mode with MVREG OFF (LP_PARAM13 bit). See note 2.
- In STANDBY mode. See note 2.
load <150 mA
1.65
1.80
1.95
V
VLPVREG
LPVREG power supply(2)
2.
In STANDBY mode, VLPVREG is observed on the V18BKP pin
In STOP mode, VLPVREG is observed on the V18, V18REG and V18BKP pins.
load <10 mA
1.30
1.40
1.50
V
tVREG_PWRUP
(1)
Voltage Regulators start-up
time (to reach 90% of final V18
value) at VDD_IO power-up
(3)
3.
Once VDD_IO has reached 3.0 V, the RSM (Regulator Startup Monitor) generates an internal RESET
during this start-up time.
VDD_IO rise
slope = 20 s/V
80
s
VDD_IO rise
slope = 20 ms/V
35
ms
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