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參數(shù)資料
| 型號： | STPC0366BTC3 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | PC Compatible Embeded Microprocessor |
| 中文描述： | PC兼容嵌入式微處理器 |
| 文件頁數(shù)： | 16/51頁 |
| 文件大?。?/td> | 726K |
| 代理商： | STPC0366BTC3 |
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PIN DESCRIPTION
16/51
Issue 1.2
driven by the target during data phase of read
transactions.
CBE#[3:0]
Bus Commands/Byte Enables. These
are the multiplexed command and byte enable
signals of the PCI bus. During the address phase
they define the command and during the data
phase they carry the byte enable information.
These pins are inputs when a PCI master other
than the STPC Consumer owns the bus and out-
puts when the STPC Consumer owns the bus.
FRAME#
Cycle Frame. This is the frame signal of
the PCIbus. It is aninput when aPCI master owns
the bus and is an output when STPC Consumer
owns the PCI bus.
TRDY#
Target Ready.This is the target ready sig-
nal of the PCI bus. It is driven as an output when
the STPC Consumer is the target of the current
bus transaction. It is used as an input when STPC
Consumer initiates a cycle on the PCI bus.
IRDY#
Initiator Ready. This is the initiator ready
signal of the PCI bus. It is used as an output when
the STPC Consumer initiates a bus cycle on the
PCI bus. It is used as an input during the PCI cy-
cles targeted to the STPC Consumer to determine
when the current PCI master is ready to complete
the current transaction.
STOP#
Stop Transaction. Stop is used to imple-
ment the disconnect, retry and abort protocol of
the PCI bus. It is used as an input for the bus cy-
cles initiated by the STPC Consumer and is used
as an output when a PCI master cycle is targeted
to the STPC Consumer.
DEVSEL#
I/O Device Select. This signal is used
as an input when the STPC Consumer initiates a
bus cycle on the PCI bus to determine if a PCI
slave device has decoded itself to be the target of
the current transaction. It is asserted as an output
either when the STPC Consumer is the target of
the current PCI transaction or when no other de-
vice asserts DEVSEL# prior to the subtractive de-
code phase of the current PCI transaction.
PAR
Parity Signal Transactions.This is the parity
signal of the PCI bus. This signal is used to guar-
antee even parity across AD[31:0], CBE#[3:0],
and PAR. This signal is driven by the master dur-
ing the address phase and data phase of write
transactions. It is driven by the target during data
phase of read transactions. (Its assertion is identi-
cal to that of theAD busdelayed by one PCI clock
cycle)
SERR#
System Error.This is the system error sig-
nal of the PCI bus. It may, if enabled, be asserted
for one PCI clock cycle if target aborts a STPC
Consumer initiated PCI transaction. Its assertion
by either the STPC Consumer or by another PCI
bus agent will trigger the assertion of NMI to the
host CPU. This is an open drain output.
LOCK#
PCI Lock.This is the lock signalof the PCI
bus and is used to implement the exclusive bus
operations when acting as a PCI target agent.
PCIREQ#[2:0]
PCI Request. This pin are the
three external PCI master requestpins. They indi-
cates to the PCI arbiter that the external agents
desire use of the bus.
PCIGNT#[2:0]
PCI Grant.These pins indicate that
the PCI bus has been granted to the master re-
questing it on its PCIREQ#.
2.2.6 ISA/IDE COMBINED ADDRESS/DATA
LA[23]/SCS3#
Unlatched Address (ISA)/Second-
ary Chip Select (IDE). This pin has two functions,
depending on whether the ISA bus is active or the
IDE bus is active.
When the ISA bus is active, this pins is ISA Bus
unlatched address bit 23 for 16-bit devices. When
ISA bus is accessed by any cycle initiated from
PCI bus, this pin is in output mode. When an ISA
bus master owns the bus, this pins is in input
mode.
When the IDE bus is active, this signals is used as
the active high secondary slave IDE chip select
signal. This signal is to be externally NANDed with
the ISAOE
#
signal before driving the IDE devices
to guarantee it is active only when ISA bus is idle.
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