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參數(shù)資料
| 型號： | STM706TDS6F |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8 |
| 封裝： | 3 X 3 MM, ROHS COMPLIANT, TSSOP-8 |
| 文件頁數(shù)： | 3/33頁 |
| 文件大?。?/td> | 695K |
| 代理商： | STM706TDS6F |
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STM706T/S/R, STM706P, STM708T/S/R
Operation
Doc ID 10518 Rev 10
3
Operation
3.1
Reset output
The STM70x supervisor asserts a reset signal to the MCU whenever VCC goes below the
reset threshold (VRST), a watchdog timeout occurs (if WDO is connected to MR), or when the
push-button reset input (MR) is taken low. RST is guaranteed to be a logic low (logic high for
STM706P and STM708T/S/R) for VCC < VRST down to VCC =1 V for TA = 0 °C to 85 °C.
During power-up, once VCC exceeds the reset threshold an internal timer keeps RST low for
the reset timeout period, trec. After this interval RST returns high.
If VCC drops below the reset threshold, RST goes low. Each time RST is asserted, it stays
low for at least the reset timeout period (trec). Any time VCC goes below the reset threshold
the internal timer clears. The reset timer starts when VCC returns above the reset threshold.
3.2
Push-button reset input
A logic low on MR asserts reset. Reset remains asserted while MR is low, and for trec (see
Figure 27) after it returns high. The MR input has an internal 40 k
Ω pull-up resistor, allowing
it to be left open if not used. This input can be driven with TTL/CMOS-logic levels or with
open-drain / collector outputs. Connect a normally open momentary switch from MR to GND
to create a manual reset function; external debounce circuitry is not required. If MR is driven
from long cables or the device is used in a noisy environment, connect a 0.1 F capacitor
from MR to GND to provide additional noise immunity. MR may float, or be tied to VCC when
not used.
3.3
Watchdog input (STM706T/S/R and STM706P)
The watchdog timer can be used to detect an out-of-control MCU. If the MCU does not
toggle the watchdog input (WDI) within tWD (1.6 s), the watchdog output pin (WDO) is
asserted. The internal 1.6s timer is cleared by either:
1.
a reset pulse, or
2.
by toggling WDI (high-to-low or low-to-high), which can detect pulses as short as 50 ns.
See Figure 28 for STM706T/S/R and STM706P.
The timer remains cleared and does not count for as long as reset is asserted. As soon as
reset is released, the timer starts counting.
3.4
Watchdog output (STM706T/S/R and STM706P)
When VCC drops below the reset threshold, WDO will go low even if the watchdog timer has
not yet timed out. However, unlike the reset output, WDO goes high as soon as VCC
exceeds the reset threshold. WDO may be used to generate a reset pulse by connecting it
to the MR input.
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相關(guān)代理商/技術(shù)參數(shù) |
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| STM706TM6E | 功能描述:監(jiān)控電路 3V Supervisor w/Battery Switchover RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| STM706TM6F | 功能描述:監(jiān)控電路 4.38V Reset Suprvsr RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| STM706TM6F-CUT TAPE | 制造商:ST 功能描述:STM706 Series 3.08 V 140 ms 3 V Surface Mount Supervisor - SOIC-8 |
| STM706YM7F | 功能描述:Supervisor Push-Pull, Totem Pole 1 Channel 8-SO 制造商:stmicroelectronics 系列:汽車級，AEC-Q100 包裝:剪切帶（CT） 零件狀態(tài):有效 類型:簡單復(fù)位/加電復(fù)位 受監(jiān)控電壓數(shù):1 輸出:推挽式，圖騰柱 復(fù)位:低有效 復(fù)位超時:最小為 140 ms 電壓 - 閾值:4.38V 工作溫度:-40°C ~ 125°C（TA） 安裝類型:表面貼裝 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商器件封裝:8-SO 標(biāo)準(zhǔn)包裝:1 |
| STM707 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5V Supervisor |
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