參數(shù)資料
型號(hào): STM32F103REH7TR
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 72 MHz, RISC MICROCONTROLLER, PBGA64
封裝: ROHS COMPLIANT, LFBGA-64
文件頁數(shù): 77/115頁
文件大小: 1225K
代理商: STM32F103REH7TR
Electrical characteristics
STM32F103xC, STM32F103xD, STM32F103xE
Table 35.
Synchronous multiplexed NOR/PSRAM read timings(1)(2)
1.
VDD_IO = V and CL = 15 pF.
2.
Based on characterization, not tested in production.
Symbol
Parameter
Min
Max
Unit
tw(CLK)
FSMC_CLK period
27.7
ns
td(CLKL-NExL)
FSMC_CLK low to FSMC_NEx low (x = 0...2)
1.5
ns
td(CLKH-NExH)
FSMC_CLK high to FSMC_NEx high (x = 0...2)
THCLK + 2
ns
td(CLKL-NADVL)
FSMC_CLK low to FSMC_NADV low
4
ns
td(CLKL-NADVH)
FSMC_CLK low to FSMC_NADV high
5
ns
td(CLKL-AV)
FSMC_CLK low to FSMC_Ax valid (x = 16...25)
0
ns
td(CLKH-AIV)
FSMC_CLK high to FSMC_Ax invalid (x = 16...25) THCLK + 2
ns
td(CLKL-NOEL)
FSMC_CLK low to FSMC_NOE low
THCLK +1
ns
td(CLKH-NOEH)
FSMC_CLK high to FSMC_NOE high
THCLK + 0.5
ns
td(CLKL-ADV)
FSMC_CLK low to FSMC_AD[15:0] valid
12
ns
td(CLKL-ADIV)
FSMC_CLK low to FSMC_AD[15:0] invalid
0
ns
tsu(ADV-CLKH)
FSMC_A/D[15:0] valid data before FSMC_CLK
high
6
ns
th(CLKH-ADV)
FSMC_A/D[15:0] valid data after FSMC_CLK hig
THCLK – 10
ns
tsu(NWAITV-CLKH) FSMC_NWAIT valid before FSMC_CLK high
8
ns
th(CLKH-NWAITV) FSMC_NWAIT valid after FSMC_CLK high
6
ns
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STM32F103REH7XXX 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:High-density performance line ARM-based 32-bit MCU with 256 to 512KB Flash, USB, CAN, 11 timers, 3 ADCs, 13 communication interfaces
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