參數(shù)資料
型號: STM32F101R8T6XXX
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 36 MHz, RISC MICROCONTROLLER, PQFP64
封裝: 10 X 10 MM, ROHS COMPLIANT, LQFP-64
文件頁數(shù): 59/81頁
文件大?。?/td> 988K
代理商: STM32F101R8T6XXX
Electrical characteristics
STM32F101x8, STM32F101xB
Doc ID 13586 Rev 12
5.3.16
12-bit ADC characteristics
Unless otherwise specified, the parameters given in Table 41 are derived from tests
performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage
conditions summarized in Table 8.
Note:
It is recommended to perform a calibration after each power-up.
Table 41.
ADC characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDDA
Power supply
2.4
3.6
V
VREF+
Positive reference voltage
2.4
VDDA
V
IVREF
Current on the VREF input
pin
160(1)
A
fADC
ADC clock frequency
0.6
14
MHz
fS
(2)
Sampling rate
0.05
1
MHz
fTRIG
External trigger frequency
fADC = 14 MHz
823
kHz
17
1/fADC
VAIN
Conversion voltage range(3)
0 (VSSA or VREF-
tied to ground)
VREF+
V
RAIN
External input impedance
Table 42 for details
50
k
Sampling switch resistance
1
k
Internal sample and hold
capacitor
8pF
Calibration time
fADC = 14 MHz
5.9
s
83
1/fADC
tlat
Injection trigger conversion
latency
fADC = 14 MHz
0.214
s
3(4)
1/fADC
tlatr
Regular trigger conversion
latency
fADC = 14 MHz
0.143
s
1/fADC
tS
Sampling time
fADC = 14 MHz
0.107
17.1
s
1.5
239.5
1/fADC
tSTAB
Power-up time
0
1
s
tCONV
Total conversion time
(including sampling time)
fADC = 14 MHz
1
18
s
14 to 252 (tS for sampling +12.5 for
successive approximation)
1/fADC
1.
Based on characterization results, not tested in production.
2.
Guaranteed by design, not tested in production.
3.
VREF+ can be internally connected to VDDA and VREF- can be internally connected to VSSA, depending on the package.
Refer to Section 3: Pinouts and pin description for further details.
4.
For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 41.
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