參數(shù)資料
型號: STM32F101R6T6AXX
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 36 MHz, RISC MICROCONTROLLER, PQFP64
封裝: 10 X 10 MM, 0.50 MM PITCH, ROHS COMPLIANT, LQFP-64
文件頁數(shù): 51/75頁
文件大?。?/td> 1552K
代理商: STM32F101R6T6AXX
STM32F101x6, STM32F101x8, STM32F101xB
Electrical characteristics
SPI interface characteristics
Unless otherwise specified, the parameters given in Table 41 are derived from tests
performed under ambient temperature, fPCLKx frequency and VDD supply voltage conditions
summarized in Table 8.
Refer to Section 5.3.12: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO).
Table 41.
SPI characteristics(1)
1.
Remapped SPI1 characteristics to be determined.
Symbol
Parameter
Conditions
Min
Max
Unit
fSCK
1/tc(SCK)
SPI clock frequency
Master mode
0
18
MHz
Slave mode
0
18
tr(SCK)
tf(SCK)
SPI clock rise and fall
time
Capacitive load: C = 30 pF
8
ns
tsu(NSS)
(2)
2.
Values based on design simulation and/or characterization results, and not tested in production.
NSS setup time
Slave mode
4 tPCLK
th(NSS)
NSS hold time
Slave mode
18
tw(SCKH)
tw(SCKL)
SCK high and low time
Master mode, fPCLK = 36 MHz,
presc = 4
50
60
tsu(MI)
Data input setup time
Master mode
SPI1
1
SPI2
5
tsu(SI)
Data input setup time
Slave mode
1
th(MI)
Data input hold time
Master mode
SPI1
1
SPI2
5
th(SI)
Data input hold time
Slave mode
3
ta(SO)
(2)(3)
3.
Min time is for the minimum time to drive the output and the max time is for the maximum time to validate
the data.
Data output access time
Slave mode, fPCLK = 36 MHz,
presc = 4
055
Slave mode, fPCLK = 24 MHz
0
4 tPCLK
tdis(SO)
(2)(4)
4.
Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put
the data in Hi-Z
Data output disable time Slave mode
10
tv(SO)
Data output valid time
Slave mode (after enable edge)
25
tv(MO)
Data output valid time
Master mode (after enable
edge)
3
th(SO)
Data output hold time
Slave mode (after enable edge)
25
th(MO)
Master mode (after enable
edge)
4
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