參數(shù)資料
型號: STK22C48W45I
廠商: Electronic Theatre Controls, Inc.
英文描述: 2K x 8 AutoStore⑩ nvSRAM QuantumTrap⑩ CMOS Nonvolatile Static RAM
中文描述: 2K × 8自動存儲非易失QuantumTrap⑩⑩的CMOS非易失性靜態(tài)隨機存儲器
文件頁數(shù): 4/11頁
文件大小: 194K
代理商: STK22C48W45I
STK22C48
December 2002
4
Document Control # ML0004 rev 0.0
SRAM WRITE CYCLES #1 & #2
(V
CC
= 5.0V
±
10%)
e
Note j:
Note k:
Note l:
SRAM WRITE CYCLE #1:
W Controlled
k, l
If W is low when E goes low, the outputs remain in the high-impedance state.
E or W must be
V
IH
during address transitions.
HSB must be high during SRAM WRITE cycles.
SRAM WRITE CYCLE #2:
E Controlled
k, l
NO.
SYMBOLS
PARAMETER
STK22C48-25
STK22C48-35
STK22C48-45
UNITS
#1
#2
Alt.
MIN
MAX
MIN
MAX
MIN
MAX
12
t
AVAV
t
AVAV
t
WC
Write Cycle Time
25
35
45
ns
13
t
WLWH
t
WLEH
t
WP
Write Pulse Width
20
25
30
ns
14
t
ELWH
t
ELEH
t
CW
Chip Enable to End of Write
20
25
30
ns
15
t
DVWH
t
DVEH
t
DW
Data Set-up to End of Write
10
12
15
ns
16
t
WHDX
t
EHDX
t
DH
Data Hold after End of Write
0
0
0
ns
17
t
AVWH
t
AVEH
t
AW
Address Set-up to End of Write
20
25
30
ns
18
t
AVWL
t
AVEL
t
AS
Address Set-up to Start of Write
0
0
0
ns
19
t
WHAX
t
EHAX
t
WR
Address Hold after End of Write
0
0
0
ns
20
t
WLQZ i, j
t
WZ
Write Enable to Output Disable
10
13
15
ns
21
t
WHQX
t
OW
Output Active after End of Write
5
5
5
ns
PREVIOUS DATA
DATA OUT
E
ADDRESS
12
t
AVAV
W
16
t
WHDX
DATA IN
19
t
WHAX
13
t
WLWH
18
t
AVWL
17
t
AVWH
DATA VALID
20
t
WLQZ
15
t
DVWH
HIGH IMPEDANCE
21
t
WHQX
14
t
ELWH
DATA OUT
E
ADDRESS
12
t
AVAV
W
DATA IN
13
t
WLEH
17
t
AVEH
DATA VALID
HIGH IMPEDANCE
14
t
ELEH
18
t
AVEL
15
t
DVEH
19
t
EHAX
16
t
EHDX
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