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參數(shù)資料
| 型號(hào)： | ST92F120V1 |
| 英文描述： | 8/16-BIT FLASH MCU FAMILY WITH RAM. EEPROM AND J1850 BLPD |
| 中文描述： | 16位產(chǎn)品系列閃存微控制器與內(nèi)存。 EEPROM和J1850 BLPD |
| 文件頁(yè)數(shù)： | 243/324頁(yè) |
| 文件大?。?/td> | 3655K |
| 代理商： | ST92F120V1 |
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J1850 Byte Level Protocol Decoder (JBLPD)
J1850 BYTE LEVEL PROTOCOL DECODER
(Cont’d)
Transmitting a Type 2 IFR
The user program will decide to transmit an IFR
type 2 byte in response to a message which is cur-
rently being received (See
Figure 4
). It does so by
writing the IFR2 opcode to the TXOP register.
Transmitting IFR data type 2 requires only a single
write of the TXOP register with the IFR2 opcode
set. The MLC[3:0] bits can also be set to check for
message length errors. If no error conditions (IBD,
IFD, TRA, RBRK or CRCE) exist to prevent trans-
mission, the JBLPD will transmit out the contents
of the PADDR register at the next EOD nominal
time period or after an EOD minimum time period if
a rising edge is detected on the filtered VPWI line
signifying another transmitter beginning early. The
NB1 symbol precedes the PADDR register value
and is followed with an EOF delimiter. The TRDY
flag will be cleared on the write of the TXOP regis-
ter. The TRDY bit is set once the NB1 begins
transmitting.
Lost arbitration for this case is a normal occur-
rence since type 2 IFR data is made up of single
bytes from multiple responders. If arbitration is lost
the VPWO line is released and the JBLPD waits
until the byte on the VPWI line is completed. Note
that the IFR that did make it out on the bus will be
received in the RXDATA register if it is not put into
sleep mode. Then, the JBLPD re-attempts to send
its physical address immediately after the end of
the last byte. The TLA bit is not set if arbitration is
lost and the user program does not need to re-
queue data or an opcode. The JBLPD will re-at-
tempt to send its PADDR register contents until it
successfully does so or the 12-byte frame maxi-
mum is reached if NFL=0. If NFL=1, then re-at-
tempts to send an lFR2 are executed until can-
celled by the CANCEL opcode or a JBLPD disa-
ble. Note that for the transmitter to synchronize to
the incoming signals of a frame, an IFR should be
queued before an EODM is received for the
present frame.
Transmitting a Type 3 lFR Data String
The user program will decide to transmit an IFR
type 3 byte string in response to a message which
is currently being received (See
Figure 5
). It does
so by writing the IFR3 or IFR3+CRC opcode to the
TXOP register. Transmitting IFR data type 3 is
similar to transmitting a message, in that the TX-
DATA register is written with the first data byte fol-
lowed by a TXOP register write. For a single data
byte IFR3 transmission, the TXOP register would
be written with IFR3+CRC opcode set. The
MLC[3:0] bits can also be set to a proper value to
check for message length errors before enabling
the IFR transmit.
If no error conditions (IBD, IFD, TRA, RBRK or
CRCE) exist to prevent transmission, the JBLPD
will wait for an EOD nominal time period on the fil-
tered VPWI line (or for at least an EOD minimum
time followed by a rising edge signifying another
transmitter beginning early) at which time data is
transferred from the TXDATA register to the trans-
mit shift register. The TRDY bit is set since the TX-
DATA register is empty. A NB0 symbol is output
on the VPWO line followed by the data byte and
possibly the CRC byte if a IFR3+CRC opcode was
set. Once the first IFR3 byte has been successfully
transmitted, successive IFR3 bytes are sent with
TXDATA/TXOP write sequences where the
MLC[3:O] bits are don’t cares. The final byte in the
IFR3 string must be transmitted with the
IFR3+CRC opcode to trigger the JBLPD to ap-
pend the CRC byte to the string. The user program
may queue up the next message opcode se-
quence once the TRDY bit has been set.
Although arbitration should never be lost for data
in the IFR portion of a type 3 frame, higher priority
messages are always honoured under the rules of
arbitration. If arbitration is lost then the block
should relinquish the bus by taking the VPWO line
to the passive state. In this case the TLA bit in the
STATUS register is set, and an interrupt will be
generated if enabled. Note also, that the IFR data
that did make it out on the bus will be received in
the RXDATA register if not in sleep mode. Note
that for the transmitter to synchronize to the in-
coming signals of a frame, an IFR should be
queued before an EODM is received for the cur-
rent frame.
9
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ST92F150JD | ST9 - 8/16-BIT SINGLE VOLTAGE FLASH MCU FAMILY WITH RAM. E3 TM (EMULATED EEPROM). CAN 2.0B AND J1850 BLPD |
| ST92F150JV1 | Microcontroller |
| ST93C06CB1 | Microwire Serial EEPROM |
| ST93C06CB3 | Microwire Serial EEPROM |
| ST93C06CB6 | Microwire Serial EEPROM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST92F120V1Q7 | 功能描述:8位微控制器 -MCU Flash 128K SPI/I2C RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| ST92F120V9Q7 | 功能描述:8位微控制器 -MCU RO 511-ST92F150CV1QB RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| ST92F124R9TB | 功能描述:8位微控制器 -MCU Flash 64K SCI/SPI/I2 RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| ST92F124V1QB | 功能描述:8位微控制器 -MCU Flash 128K 2SCI/SPI RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| ST92F124V1T6 | 功能描述:8位微控制器 -MCU 8/16-BIT SINGLE VOLT RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
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