參數(shù)資料
型號(hào): ST78C36A
廠商: Exar Corporation
英文描述: ECP/EPP Parallel Printer Port with 16 Byte FIFO(ECP/EPP并行打印機(jī)端口(帶16字節(jié)先進(jìn)先出))
中文描述: 支持ECP / EPP并行打印機(jī)端口(支持ECP / EPP并行打印機(jī)端口(帶16字節(jié)先進(jìn)先出),16字節(jié)FIFO)
文件頁數(shù): 11/27頁
文件大?。?/td> 204K
代理商: ST78C36A
ST78C36/36A
6-31
Rev. 4.20
MODE
NAME
DESCRIPTION
000
SPP
Standard, output only. DCR
Bit-5 is forced to “0”.
Bi-directional PS/2 parallel
port. FIFO is disabled
FIFOed, output only. DCR
Bit-5 is forced to “0”.
ECP FIFOed port with RLE
de-compression. FIFO direc-
tion is controlled by DCR Bit-
5.
EPP mode.
reserved
FIFO test mode. FIFO is ac-
cessible via TFIFO register.
001
PS2
010
PPF
011
ECP
100
101
110
EPP
-
TST
111
CFG
Configuration A/B register
enable.
OPERATION
SPP MODE
This is ECR mode 000 (system RESET mode).
In this output-only mode the host data is registered to
PD[7:0] at the trailing edge of -IOW; PDIR is driven
low; -STROBE, -AUTOFD, INIT, and -SLCTIN are
open-drain; and all timing is managed by the host
through DSR and DCR registers.
PS2 MODE
This is ECR mode 001.
In this bi-directional mode the host output data is
registered to PD[7:0] at the trailing edge of -IOW,
PDIR is driven by DIR to allow peripheral data input,
-AUTOFD, INIT, and -SLCTIN are totem-pole, and all
timing is managed by the host through DSR and DCR
registers.
PPF MODE
This is ECR mode 010.
In this output-only mode the host data is written to the
FIFO with I/O writes to address 400 or by DMA writes;
PDIR is driven low; -AUTOFD, INIT, and -SLCTIN are
totem-pole.
FIFO data is automatically registered to PD[7:0]
whenever the FIFO-E bit is low (data available), and
timing is generated by controller logic that hand-
shakes -STROBE (controller) with BUSY (peripheral).
ECP MODE
This is ECR mode 011.
In this bi-directional mode the host data is written to
the FIFO with I/O writes to address 000, 400 or DMA;
PDIR is driven by DIR (can only be set in ECR mode
001); -AUTOFD, INIT, and -SLCTIN are totem-pole.
I/O writes to address 000 will write a low into the FIFO
tag bit, while I/O writes to address 400 or DMA will
insert a high.
ECP FORWARD MODE (PDIR = 0)
FIFO data is automatically registered to PD[7:0]
whenever the FIFO-E bit is low (data available), and
timing is generated by controller logic that hand-
shakes -STROBE (controller) with BUSY (peripheral).
Data from the FIFO tag bit is output on -AUTOFD after
being registered simultaneous with FIFO data.
ECP REVERSE MODE (PDIR = 1)
PD[7:0] data and BUSY are latched into the FIFO and
tag bit respectively at the trailing edge of -AUTOFD if
FIFO-F = 0. Timing is generated by controller logic
that handshakes -ACK (peripheral) with -AUTOFD
(controller).
EPP MODE
This is ECR mode 100.
In this bi-directional mode, I/O writes will latch host
output data at the trailing edge of -IOW, and peripheral
input data will be latched at the trailing edge of -
SLCTIN or -AUTOFD. PDIR, and -STROBE are
driven by the state of -IOW (DCR bits 5 and 0 must be
set low); -AUTOFD, INIT, and -SLCTIN are totem-
pole.
EPP mode allows buffered access between the PC
bus and the peripheral with timing provided by the
peripheral via BUSY handshake into IOCHRDY. I/O
cycles with address 003 - 007 will immediately drive
IOCHRDY low. -STROBE will go low and PD[7:0] is
allowed to change (write cycles) after BUSY has been
low for at least 60n second. (this delay may have
elapsed prior to cycle initiation), immediately followed
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