參數(shù)資料
型號: ST72C124J2
英文描述: 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY. ADC. 16-BIT TIMERS. SPI. SCI INTERFACES
中文描述: 8位單電壓閃存微控制器。 ADC的。 16位定時器。的SPI。脊髓損傷接口
文件頁數(shù): 76/153頁
文件大小: 1988K
代理商: ST72C124J2
ST72334J/N, ST72314J/N, ST72124J
29/153
RESET SEQUENCE MANAGER (Cont’d)
9.2.2 Asynchronous External RESET pin
The RESET pin is both an input and an open-drain
output with integrated RON weak pull-up resistor.
This pull-up has no fixed value but varies in ac-
cordance with the input voltage. It can be pulled
low by external circuitry to reset the device. See
electrical characteristics section for more details.
A RESET signal originating from an external
source must have a duration of at least th(RSTL)in in
order to be recognized. This detection is asynchro-
nous and therefore the MCU can enter reset state
even in HALT mode.
The RESET pin is an asynchronous signal which
plays a major role in EMS performance. In a noisy
environment, it is recommended to follow the
guidelines mentioned in the electrical characteris-
tics section.
Two RESET sequences can be associated with
this RESET source: short or long external reset
pulse (see Figure 16).
Starting from the external RESET pulse recogni-
tion, the device RESET pin acts as an output that
is pulled low during at least tw(RSTL)out.
9.2.3 Internal Low Voltage Detection RESET
Two different RESET sequences caused by the in-
ternal LVD circuitry can be distinguished:
s
Power-On RESET
s
Voltage Drop RESET
The device RESET pin acts as an output that is
pulled low when VDD<VIT+ (rising edge) or
VDD<VIT- (falling edge) as shown in Figure 16.
The LVD filters spikes on VDD larger than tg(VDD) to
avoid parasitic resets.
9.2.4 Internal Watchdog RESET
The RESET sequence generated by a internal
Watchdog counter overflow is shown in Figure 16.
Starting from the Watchdog counter underflow, the
device RESET pin acts as an output that is pulled
low during at least tw(RSTL)out.
Figure 16. RESET Sequences
VDD
0000000000
000
RUN
RESET PIN
EXTERNAL
WATCHDOG
DELAY
VIT+
VIT-
th(RSTL)in
tw(RSTL)out
RUN
00000000000
000
DELAY
th(RSTL)in
00000000000
000
DELAY
WATCHDOG UNDERFLOW
tw(RSTL)out
RUN
0000000000
0000
DELAY
RUN
RESET
SOURCE
SHORT EXT.
RESET
LVD
RESET
LONG EXT.
RESET
WATCHDOG
RESET
0000000000000
0000000000000 INTERNAL RESET (4096 TCPU)
FETCH VECTOR
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