參數(shù)資料
型號: ST72C104G2M5
英文描述: 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY. ADC. 16-BIT TIMERS. SPI.
中文描述: 8位單電壓閃存微控制器。 ADC的。 16位定時器。的SPI。
文件頁數(shù): 74/140頁
文件大?。?/td> 1349K
代理商: ST72C104G2M5
ST72104G, ST72215G, ST72216G, ST72254G
39/140
12 ON-CHIP PERIPHERALS
12.1 WATCHDOG TIMER (WDG)
12.1.1 Introduction
The Watchdog timer is used to detect the occur-
rence of a software fault, usually generated by ex-
ternal interference or by unforeseen logical condi-
tions, which causes the application program to
abandon its normal sequence. The Watchdog cir-
cuit generates an MCU reset on expiry of a pro-
grammed time period, unless the program refresh-
es the counter’s contents before the T6 bit be-
comes cleared.
12.1.2 Main Features
s
Programmable timer (64 increments of 12288
CPU cycles)
s
Programmable reset
s
Reset (if watchdog activated) when the T6 bit
reaches zero
s
Optional
reset
on
HALT
instruction
(configurable by option byte)
s
Hardware Watchdog selectable by option byte.
12.1.3 Functional Description
The counter value stored in the CR register (bits
T6:T0), is decremented every 12,288 machine cy-
cles, and the length of the timeout period can be
programmed by the user in 64 increments.
If the watchdog is activated (the WDGA bit is set)
and when the 7-bit timer (bits T6:T0) rolls over
from 40h to 3Fh (T6 becomes cleared), it initiates
a reset cycle pulling low the reset pin for typically
500ns.
The application program must write in the CR reg-
ister at regular intervals during normal operation to
prevent an MCU reset. The value to be stored in
the CR register must be between FFh and C0h
(see Table 11 . Watchdog Timing (fCPU = 8
MHz)):
– The WDGA bit is set (watchdog enabled)
– The T6 bit is set to prevent generating an imme-
diate reset
– The T5:T0 bits contain the number of increments
which represents the time delay before the
watchdog produces a reset.
Figure 25. Watchdog Block Diagram
RESET
WDGA
7-BIT DOWNCOUNTER
fCPU
T6
T0
CLOCK DIVIDER
WATCHDOG CONTROL REGISTER (CR)
÷12288
T1
T2
T3
T4
T5
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