參數(shù)資料
型號: ST72C104G2B7
英文描述: 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY. ADC. 16-BIT TIMERS. SPI.
中文描述: 8位單電壓閃存微控制器。 ADC的。 16位定時器。的SPI。
文件頁數(shù): 51/140頁
文件大?。?/td> 1349K
代理商: ST72C104G2B7
ST72104G, ST72215G, ST72216G, ST72254G
18/140
7.1 LOW VOLTAGE DETECTOR (LVD)
To allow the integration of power management
features in the application, the Low Voltage Detec-
tor function (LVD) generates a static reset when
the VDD supply voltage is below a VIT- reference
value. This means that it secures the power-up as
well as the power-down keeping the ST7 in reset.
The VIT- reference value for a voltage drop is lower
than the VIT+ reference value for power-on in order
to avoid a parasitic reset when the MCU starts run-
ning and sinks current on the supply (hysteresis).
The LVD Reset circuitry generates a reset when
VDD is below:
–VIT+ when VDD is rising
–VIT- when VDD is falling
The LVD function is illustrated in the Figure 9.
Provided the minimum VDD value (guaranteed for
the oscillator frequency) is above VIT-, the MCU
can only be in two modes:
– under full software control
– in static safe reset
In these conditions, secure operation is always en-
sured for the application without the need for ex-
ternal reset hardware.
During a Low Voltage Detector Reset, the RESET
pin is held low, thus permitting the MCU to reset
other devices.
Notes:
1. The LVD allows the device to be used without
any external RESET circuitry.
2. Three different reference levels are selectable
through the option byte according to the applica-
tion requirement.
LVD application note
Application software can detect a reset caused by
the LVD by reading the LVDRF bit in the CRSR
register.
This bit is set by hardware when a LVD reset is
generated and cleared by software (writing zero).
Figure 9. Low Voltage Detector vs Reset
VDD
VIT+
RESET
VIT-
Vhyst
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