參數(shù)資料
型號(hào)： ST72521BM6
英文描述： ST72521B - 80/64-PIN 8-BIT MCU WITH 32 TO 60K ROM. FIVE TIMERS. SPI. SCI. I2C. CAN INTERFACE
中文描述： ST72521B - 80/64-PIN 8位32至60,000 ROM的微處理器。 5個(gè)定時(shí)器。的SPI。脊髓損傷。 I2C總線。 CAN接口
文件頁(yè)數(shù)： 129/198頁(yè)
文件大?。?/td> 2504K
代理商： ST72521BM6
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ST72521B
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CONTROLLER AREA NETWORK
(Cont’d)
–
RESYNC
. The resynchronization mode is used
to find the correct entry point for starting trans-
mission or reception after the node has gone
asynchronous either by going into the STANDBY
or bus-off states.
Resynchronization is achieved when 128 se-
quences of 11 recessive bits have been moni-
tored unless the node is not bus-off and the
FSYN bit in the CSR register is set in which case
a single sequence of 11 recessive bits needs to
be monitored.
–
IDLE
. The CAN controller looks for one of the fol-
lowing events: the RUN bit is reset, a Start Of
Frame appears on the CAN bus or the DATA7
register of the currently active page is written to.
–
TRANSMISSION
. Once the LOCK bit of a Buffer
Control/Status Register (BCSRx) has been set
and read back as such, a transmit job can be
submitted by writing to the DATA7 register. The
message with the highest priority will be transmit-
ted as soon as the CAN bus becomes idle.
Among those messages with a pending trans-
mission request, the highest priority is given to
Buffer 3 then 2 and 1. If the transmission fails due
to a lost arbitration or to an error while the NRTX
bit of the CSR register is reset, then a new trans-
mission attempt is performed . This goes on until
the transmission ends successfully or until the
job is cancelled by unlocking the buffer, by set-
ting the NRTX bit or if the node ever enters bus-
off or if a higher priority message becomes pend-
ing. The RDY bit in the BCSRx register, which
was set since the job was submitted, gets reset.
When a transmission is in progress, the BUSY bit
in the BCSRx register is set. If it ends successful-
ly then the TXIF bit in the Interrupt Status Regis-
ter (ISR) is set, else the TEIF bit is set. An
interrupt is generated in either case provided the
TXIE and TEIE bits of the ICR register are set.
The ETX bit in the same register is used to get an
early transmit interrupt and to automatically un-
lock the transmitting buffer upon successful com-
pletion of its job. This enables the CPU to get a
new transmit job pending by the end of the cur-
rent transmission while always leaving two buff-
ers available for reception. An uninterrupted
stream of messages may be transmitted in this
way at no overrun risk.
Note 1:
Setting the SRTE bit of the CSR register
allows transmitted messages to be simultane-
ously received when they pass the acceptance
filtering. This is particularly useful for checking
the integrity of the communication path.
Note 2:
When the ETX bit is reset, the buffer with
the highest priority and with a pending transmis-
sion request is always transmitted. When the
ETX bit is set, once a buffer participates in the ar-
bitration phase, it is sent until it wins the arbitra-
tion even if another transmission is requested
from a buffer with a higher priority.
–
RECEPTION
. Once the CAN controller has syn-
chronized itself onto the bus activity, it is ready
for reception of new messages. Every incoming
message gets its identifier compared to the ac-
ceptance filters. If the bitwise comparison of the
selected bits ends up with a match for at least
one of the filters then that message is elected for
reception and a target buffer is searched for. This
buffer will be the first one - order is 1 to 3 - that
has the LOCK and RDY bits of its BCSRx regis-
ter reset.
– When no such buffer exists then an overrun
interrupt is generated if the ORIE bit of the ICR
register has been set. In this case the identifi-
er of the last message is made available in the
Last Identifier Register (LIDHR and LIDLR) at
least until it gets overwritten by a new identifi-
er picked-up from the bus.
– When a buffer does exist, the accepted mes-
sage gets written into it, the ACC bit in the
BCSRx register gets the number of the match-
ing filter, the RDY and RXIF bits get set and an
interrupt is generated if the RXIE bit in the ISR
register is set.
Up to three messages can be automatically
received without intervention from the CPU
because each buffer has its own set of status
bits, greatly reducing the reactiveness require-
ments in the processing of the receive inter-
rupts.
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