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參數(shù)資料
| 型號(hào)： | ST72344K4T6 |
| 廠商： | STMICROELECTRONICS |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER, PQFP32 |
| 封裝： | 7 X 7 MM, ROHS COMPLIANT, TQFP-32 |
| 文件頁(yè)數(shù)： | 212/246頁(yè) |
| 文件大?。?/td> | 2016K |
| 代理商： | ST72344K4T6 |
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Power-saving modes
ST72344xx, ST72345xx
Halt mode recommendations
●
Make sure that an external event is available to wake up the microcontroller from Halt
mode.
●
When using an external interrupt to wake up the microcontroller, reinitialize the
corresponding I/O as “Input Pull-up with Interrupt” before executing the HALT
instruction. The main reason for this is that the I/O may be wrongly configured due to
external interference or by an unforeseen logical condition.
●
For the same reason, reinitialize the level sensitiveness of each external interrupt as a
precautionary measure.
●
The opcode for the HALT instruction is 0x8E. To avoid an unexpected HALT instruction
due to a program counter failure, it is advised to clear all occurrences of the data value
0x8E from memory. For example, avoid defining a constant in ROM with the value
0x8E.
●
As the HALT instruction clears the interrupt mask in the CC register to allow interrupts,
the user may choose to clear all pending interrupt bits before executing the HALT
instruction. This avoids entering other peripheral interrupt routines after executing the
external interrupt routine corresponding to the wake-up event (reset or external
interrupt).
9.5
Active-halt mode
Active-halt mode is the lowest power consumption mode of the MCU with a real-time clock
available. It is entered by executing the ‘HALT’ instruction when MCC/RTC interrupt enable
flag (OIE bit in MCCSR register) is set and when the AWUEN bit in the AWUCSR register is
cleared (see Register description on page 72).
The MCU can exit Active-halt mode on reception of the RTC interrupt and some specific
interrupts (see Table 16: Interrupt mapping on page 59) or a reset. When exiting Active-halt
mode by means of a reset a 4096 or 256 CPU cycle delay occurs (depending on the option
byte). After the start up delay, the CPU resumes operation by servicing the interrupt or by
fetching the reset vector which woke it up (see Figure 31).
When entering Active-halt mode, the I[1:0] bits in the CC register are cleared to enable
interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately.
In Active-Halt mode, only the main oscillator and its associated counter (MCC/RTC) are
running to keep a wake-up time base. All other peripherals are not clocked except those
which get their clock supply from another clock generator (such as external or auxiliary
oscillator).
The safeguard against staying locked in Active-halt mode is provided by the oscillator
interrupt.
Note:
As soon as active halt is enabled, executing a HALT instruction while the Watchdog is active
does not generate a reset. This means that the device cannot spend more than a defined
delay in this power saving mode.
Table 22.
Power saving mode
MCCSR OIE bit
Power saving mode entered when HALT instruction is executed
0
Halt mode
1
Active-halt mode
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