- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄372310 > ST72121 8-bit Microcontroller with 2/4/8K Bytes In-System Programmable Flash PDF資料下載
參數(shù)資料
| 型號： | ST72121 |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-bit Microcontroller with 2/4/8K Bytes In-System Programmable Flash |
| 中文描述： | 8位微控制器與2/4/8K字節(jié)在系統(tǒng)可編程閃存 |
| 文件頁數(shù)： | 24/93頁 |
| 文件大?。?/td> | 915K |
| 代理商： | ST72121 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁當(dāng)前第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁
24/93
ST72E121 ST72T121
5 ON-CHIP PERIPHERALS
5.1 I/O PORTS
5.1.1 Introduction
The I/O ports offer different functional modes:
– transfer of data through digital inputs and outputs
and for specific pins:
– analog signal input (ADC)
– alternate signal input/output for the on-chip pe-
ripherals.
– external interrupt generation
An I/O port is composed of up to 8 pins. Each pin
can be programmed independently as digital input
(with or without interrupt generation) or digital out-
put.
5.1.2 Functional Description
Each port is associated to 2 main registers:
– Data Register (DR)
– Data Direction Register (DDR)
and some of them to an optional register:
– Option Register (OR)
Each I/O pin may be programmed using the corre-
sponding register bits in DDR and OR registers: bit
X corresponding to pin X of the port. The same cor-
respondence is used for the DR register.
The following description takes into account the
OR register, for specific ports which do not provide
this register refer to the I/O Port Implementation
Section 5.1.3
. The generic I/O block diagram is
shown on
Figure 19
.
5.1.2.1 Input Modes
The input configuration is selected by clearing the
corresponding DDR register bit.
In this case, reading the DR register returns the
digital value applied to the external I/O pin.
Different input modes can be selected by software
through the OR register.
Notes
:
1. All the inputs are triggered by a Schmitt trigger.
2. When switching from input mode to output
mode, the DR register should be written first to
output the correct value as soon as the port is con-
figured as an output.
Interrupt function
When an I/O is configured in Input with Interrupt,
an event on this I/O can generate an external In-
terrupt request to the CPU. The interrupt polarity is
given independently according to the description
mentioned in the Miscellaneous register or in the
interrupt register (where available).
Each pin can independently generate an Interrupt
request.
Each external interrupt vector is linked to a dedi-
cated group of I/O port pins (see Interrupts sec-
tion). If several input pins are configured as inputs
to the same interrupt vector, their signals are logi-
cally ANDed before entering the edge/level detec-
tion block. For this reason if one of the interrupt
pins is tied low, it masks the other ones.
5.1.2.2 Output Mode
The pin is configured in output mode by setting the
corresponding DDR register bit.
In this mode, writing “0” or “1” to the DR register
applies this digital value to the I/O pin through the
latch. Then reading the DR register returns the
previously stored value.
Note
: In this mode, the interrupt function is disa-
bled.
5.1.2.3 Digital Alternate Function
When an on-chip peripheral is configured to use a
pin, the alternate function is automatically select-
ed. This alternate function takes priority over
standard I/O programming. When the signal is
coming from an on-chip peripheral, the I/O pin is
automatically configured in output mode (push-pull
or open drain according to the peripheral).
When the signal is going to an on-chip peripheral,
the I/O pin has to be configured in input mode. In
this case, the pin’s state is also digitally readable
by addressing the DR register.
Notes:
1. Input pull-up configuration can cause an unex-
pected value at the input of the alternate peripher-
al input.
2. When the on-chip peripheral uses a pin as input
and output, this pin must be configured as an input
(DDR = 0).
Warning:
The alternate function must not be acti-
vated as long as the pin is configured as input with
interrupt, in order to avoid generating spurious in-
terrupts.
24
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ST72121J2 | 8-bit Microcontroller with 2/4/8K Bytes In-System Programmable Flash |
| ST72121J4 | 8-bit Microcontroller with 2/4/8K Bytes In-System Programmable Flash |
| ST72171 | 8-BIT MCU WITH 8K FLASH. ADC. WDG. SPI. SCI. TIMERS SPGAS (SOFTWARE PROGRAMMABLE GAIN AMPLIFIERS). OP-AMP |
| ST733C04LFL0 | Fuse Holder; Fuse Size/Group:Micro; Mounting Type:PC Board; Body Material:Thermoplastic; Contact Material:Copper Alloy; Contact Plating:Tin; Current Rating:5A; Leaded Process Compatible:Yes; Terminal Type:Push-On |
| ST733C04LFM0 | Fuse Holder; Leaded Process Compatible:Yes; Mounting Type:Panel Mount RoHS Compliant: Yes |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST72121J2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT MICROCONTROLLER (MCU) WITH 8 TO 16 K ROM/OTP/EPROM. 384 TO 512 BYTES RAM. WDG. SCI. SPI & 2 TIMERS - SDIP42. TQFP44 |
| ST72121J4 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT MICROCONTROLLER (MCU) WITH 8 TO 16 K ROM/OTP/EPROM. 384 TO 512 BYTES RAM. WDG. SCI. SPI & 2 TIMERS - SDIP42. TQFP44 |
| ST72124J | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES |
| ST72124J2 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES |
| ST72124J2B | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。