參數(shù)資料
型號: ST70136B
廠商: 意法半導(dǎo)體
英文描述: CPE ADSL ANALOG FRONT END
中文描述: 終端ADSL模擬前端
文件頁數(shù): 11/24頁
文件大?。?/td> 361K
代理商: ST70136B
ST70136
11/24
4.7.1.3 - Special Features Configuration
This register is located at the address “010” and is used to configure different blocks.
Table 4 :
Adsl Configuration (address [b2:b0]=”010”)
4.7.1.4 - VCXO Control
Table 5 :
VCXO DAC Value (address [b2:b0]=”011”)
4.7.1.5 - Test Only Registers
They are presently located at address “100” to “101”.
4.7.1.6 - Tone Detection Threshold Setting Register
Table 6 :
Tone Detection Threshold Setting Register (address [b2:b0]=”110”)
4.7.1.7 - Status Register & tone detector
This register can be used in the case of read / write registers.
Table 7 :
Status & Tone Detector Register (address [b2:b0]=”111”)
Note:
1. R/W_clear: bit is resetted to 0 by writing 0.
Name
Pos.
Type
Def.
Description
Reserved
VCO-DAC
14.13
12
R/W
R/W
00
1
Reserved
Enable the VCO DAC
1: enabled
0: disabled
Other
FVCXO
11.4
3
R/W
R/W
0..0
0
Reserved
Filtered VCXO output
1 : filtered
0 : not filtered
Name
pos.
type
def.
Description
DAC value
14..7
R/W
80H
8 bits for VCO DAC.
0...0 = min. current
1...1 = max current.
Others
6..3
R/W
0000
Reserved
Name
Pos.
Type
Def.
Description
Threshold Level
Reserved
14..5
4.3
R/W
R/W
1000000000
00
Set the threshold of the tone detector
Reserved
Name
Pos.
Type
Def.
Description
Receiver Clip indicator
14
R/W_clear
1
R/W_clear
R/W
0
1: Receive Clipping occurred
Transceiver Clip indicator
Sleeping Mode
13
12
0
0
1: Transmit Clipping occurred
0: disable tone detector in power down
1: enable tone detector in power down
Tone detector frequency setting
0: standard ADSL (tone 40)
1: ADSL over ISDN (tone 72)
When in normal mode “0” the CTRLOUT pin is in HIZ
and don’t care for R/W and the control access register
are always writing operation whatever on R/W pin.
When in debug mode “1” the CTRLOUT and R/W pins
are operating as defined in pin description chapter.
When set all registers are set to their default value
Reserved
Tone Detector
11
R/W
0
Debug Mode
10
R/W
0
Software Reset
Reserved
9
R/W
R/W
0
8..3
0..0
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