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ST70134 - ST70135A
4/8
Discrete MultiTone Digital Modem (ST70135A)
The
DMT
modem
has
HCMOS6 (0.35
μ
m) technology. It performs PMD
(Physycal Medium Dependant) sub-layer and TC
(Transmission Convergence) sub-layer functions.
In other words we can split the chip into two
separate blocks: the first one which carries out
modem functions (PMD sub layer) and a second
one in charge of ATM framing. The chip is
controlled
and
programmed
processor and is seen as a memory mapped
device.
been
developed in
by
an
external
MODEM Functions
The modem part of the chip includes all the
necessary blocks
needed
mapping and demapping. A 14-bit code for every
carrier allows constellations with up to 16383
points. Internally, digital filters carry out Time
Equalization to reduce the effects of the inter
symbol interference. That is followed by Fast
Fourier Transform (intransmit direction an Inverse
FFT is performed) in order to change from time
domain
to
frequency
Frequency Equalization cuts down carrier by
carrier the channel distortion, signal’s amplitude
attenuation and
phase rotation. By efficient
algorithms,
this
block
ST70134’s integrated VCXO controller, the NT
crystal oscillator which comes up in an excellent
synchronisation (less than 2ppm) with ATU-C.
for
digitally
DMT
domain.
Afterwards
a
drives,
through
the
FRAMING Functions
ST70135A performs framing functions for generic
and ATM TC sub layers.
Figure 3 :
DMT Modem block diagram
ATM TC sub layer performs cell level functions:
delineation,
idle
cells
insertion/extraction, payload scrambling, Header
Error Correction (HEC) check and data frame
generation.
or
unassigned
cells
ST70135A DMT modem main features:
– Time-domain equalisation
– Rotor and frequency-domain equalisation
– Decimation, interpolation
– FFT and IFFT
– Mapping/demapping over 256 carriers
– Trelliscodingand decodingusingViterbi algorithm
– Error and noise monitoring on individual tones
– Reed-Solomon encoding and decoding
– (De) framing and (de) interleaving
– Cell HEC generation/verification
– Payload (de) scrambling
– ATM cell insertion/extraction
– Idle &/or Unassigned cell insertion/filtering
– VPI/VCI filtering
– UTOPIAinterface (Level 1 or 2)
– Microcontroller interface with 16-bit multiplexed
address/data bus and big/little endian format
supported
– JTAG test port
– Single 3.3V supply, 1.0W
– PQFP144 (28 x 28mm body, 0.65mm pitch)
FFT
Rx
DSPFE
DEMAPPER
VITERBI
CELL
BASED
FUNCT.
DE-
FRAMER
Rx
INTERF.
INTERLEAVED
FAST
SIGNALMONITORING
&FEQUPDATE & DPLL
ADSL
AFE
PMDSUBLAYER
TCSUBLAYER
ATM(UTOPIA)
IFFT
Tx
DSPFE
MAPPER
VITERBI
R/S
CODER
CELL
BASED
FUNCT.
FRAMER
Tx
INTERF.
FAST
INTERLEAVED
R/S
DECODER