參數(shù)資料
型號: ST6388
廠商: 意法半導(dǎo)體
英文描述: 8-BIT MCUs WITH ON-SCREEN-DISPLAY FOR TV TUNING
中文描述: 8位微控制器對屏幕,電視調(diào)諧顯示器
文件頁數(shù): 13/82頁
文件大?。?/td> 718K
代理商: ST6388
13/82
ST6380, ST6381, ST6382, ST6383, ST6388, ST6389
MEMORY SPACES
(Cont’d)
1.3.4
Data
Addressing
In all members of the ST638x family 64 bytes of
data RAM are directly addressable in the data
space from 80h to BFh addresses. The additional
192 bytes of RAM, the 384 bytes of EEPROM, and
the OSD RAM can be addressed using the banks
of 64 bytes located between addresses 00h and
3Fh. The selection of the bank is done by pro-
gramming the Data RAM Bank Register (DRBR)
located at the E8h address of the Data Space. In
this way each bank of RAM, EEPROM or OSD
RAM can select 64 bytes at a time. No more than
one bank should be set at a time.
Data RAM Bank Register (DRBR)
Address: E8h - Write only
Reset Value: XXh
RAM/EEPROM/OSD
RAM
DRBR7,DRBR1,DRBR0
. These bits select the
EEPROM pages.
DRBR6, DRBR5
. Each of these bits, when set, will
select one OSD RAM register page.
DRBR4,DRBR3,DRBR2
. Each of these bits, when
set, will select one RAM page.
This register is undefined after reset.
Table 5
summarizes how to set the Data RAM
Bank Register in order to select the various banks
or pages.
Caution
:
This register contains at least one write
only bit. Single bit instructions (SET, RES, INC
and DEC) should not be used.
Note
: Care is required when handling the DRBR
as it is write only. For this reason, it is not allowed
to change the DRBR contents while executing in-
terrupts drivers, as the driver cannot save and
than restore its previous content. If it is impossible
to avoid the writing of this register in interrupts
drivers, an image of this register must be saved in
a RAM location, and each time the program writes
the DRBR it writes also the image register. The im-
age register must be written first, so if an interrupt
occurs between the two instructions the DRBR is
not affected.
Table 5. Data RAM Bank Register Set-up
7
0
DRBR
7
DRBR
6
DRBR
5
DRBR
4
DRBR
3
DRBR
2
DRBR
1
DRBR
0
DRBR Value
Hex.
01h
02h
03h
81h
82h
83h
04h
08h
10h
20h
Selection
Binary
0000 0001
0000 0010
0000 0011
1000 0001
1000 0010
1000 0011
0000 0100
0000 1000
0001 0000
0010 0000
EEPROM Page 0
EEPROM Page 1
EEPROM Page 2
EEPROM Page 3
EEPROM Page 4
EEPROM Page 5
RAM Page 2
RAM Page 3
RAM Page 4
OSD Page 5
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