參數(shù)資料
型號(hào)： ST6375B1/XXX
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP42
封裝： SHRINK, PLASTIC, DIP-42
文件頁數(shù)： 28/84頁
文件大?。?/td> 861K
代理商： ST6375B1/XXX
34/84
ST6365, ST6375, ST6385 ST6367, ST6377, ST6387
4.3 SERIAL PERIPHERAL INTERFACE
The ST638x Serial Peripheral Interface (SPI) has
been designed to be cost effective and flexible in
interfacing the various peripherals in TV applica-
tions.
It maintains the software flexibility but adds hard-
ware configurations suitable to drive devices
which require a fast exchange of data. The three
pins dedicated for serial data transfer (single mas-
ter only) can operate in the following ways:
– as standard I/O lines (software configuration)
– as S-BUS or as I
2C BUS (two pins)
– as standard (shift register) SPI
When using the hardware SPI, a fixed clock rate of
62.5kHz is provided. It has to be noted that the first
bit that is output on the data line by the 8-bit shift
register is the MSB.
4.3.1 S-BUS/I2C BUS Protocol Information
The S-BUS is a three-wire bidirectional data-bus
with functional features similar to the I2C BUS. In
fact the S-BUS includes decoding of Start/Stop
conditions and the arbitration procedure in case of
multimaster system configuration (the ST638x SPI
allows a single-master only operation). The SDA
line, in the I
2C BUS represents the AND combina-
tion of SDA and SEN lines in the S-BUS. If the
SDA and the SEN lines are short-circuit connect-
ed, they appear as the SDA line of the I
2C BUS.
The Start/Stop conditions are detected (by the ex-
ternal peripherals suited to work with S-BUS/I2C
BUS) in the following way:
– On S-BUS by a transition of the SENline (1 to 0
Start, 0 to 1 Stop) while the SCL line is at high
level.
– On I
2C BUS by a transition of the SDA line (10
Start, 01Stop) while the SCL line is at high level.
Start and Stop condition are always generated by
the master (ST638x SPI can only work as single
master). The bus is busy after the start condition
and can be considered again free only when a cer-
tain time delay is left after the stop condition. In the
S-BUS configuration the SDA line is only allowed
to change during the time SCL line is low. After the
start information the SENline returns to high level
and re-mains unchanged for all the data transmis-
sion time. When the transmission is completed the
SDA line is set to high level and, at the same time,
the SEN line returns to the low level in order to
supply the stop in-formation with a low to high tran-
sition, while the SCL line is at high level. On the S-
BUS, as on the I2C BUS, each eight bit information
(byte) is followed by one acknowledged bit which
is a high level put on the SDA line by the transmit-
ter. A peripheral that acknowledges has to pull
down the SDA line during the acknowledge clock
pulse. An addressed receiver has to generate an
acknowledge after the reception of each byte; oth-
erwise the SDA line remains at the high level dur-
ing the ninth clock pulse time. In this case the mas-
ter transmitter can generate the Stop condition, via
the SEN (or SDA in I
2C BUS) line, in order to abort
the transfer.
相關(guān)PDF資料
PDF描述
ST6367B1/XXX 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP42
ST6382B1/XXX 8-BIT, MROM, MICROCONTROLLER, PDIP42
ST6386B1 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP42
ST6388B1 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP42
ST6387B1 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP42
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