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參數(shù)資料
| 型號(hào)： | ST62E65CF1 |
| 英文描述： | 8-BIT MICROCONTROLLER ( MCU ) WITH OTP. ROM. FASTROM. EPROM. A/D CONVERTER. SAFE RESET. AUTO-RELOAD TIMER. EEPROM AND SPI |
| 中文描述： | 8位微控制器（MCU）的與檢察官辦公室。光盤。 FASTROM。存儲(chǔ)器。的A / D轉(zhuǎn)換器。安全復(fù)位。自動(dòng)重加載定時(shí)器。的EEPROM和SPI |
| 文件頁數(shù)： | 51/84頁 |
| 文件大?。?/td> | 918K |
| 代理商： | ST62E65CF1 |
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ST62T53C/T60C/T63C ST62E60C
AUTO-RELOAD TIMER
(Cont’d)
AR Status Control Register 1(ARSC1)
Address: D7h
—
Read/Write
Bist 7-5 =
PS2-PS0
:
Prescaler Division Selection
Bits 2-0.
These bits determine the Prescaler divi-
sion ratio. The prescaler itself is not affected by
these bits. The prescaler division ratio is listed in the
following table:
Table 13. Prescaler Division Ratio Selection
Bit 4 =
D4
:
Reserved
. Must be kept reset.
Bit 3-2 =
SL1-SL0
:
Timer Input Edge Control Bits 1-
0.
These bits control the edge function of the Timer
input pin for external synchronization. If bit SL0 is re-
set, edge detection is disabled; if set edge detection
is enabled. If bit SL1 is reset, the AR Timer input pin
is rising edge sensitive; if set, it is falling edge sen-
sitive.
Bit 1-0 =
CC1-CC0
:
Clock Source Select Bit 1-0.
These bits select the clock source for the AR Timer
through the AR Multiplexer. The programming of
the clock sources is explained in the following
Table
14
:
Table 14. Clock Source Selection.
AR Load Register ARLR
. The ARLR load register
is used to read or write the ARTC counter register
“on the fly” (while it is counting). The ARLR regis-
ter is not affected by system reset.
AR Load Register (ARLR)
Address: DBh
—
Read/Write
Bit 7-0 =
D7-D0
:
Load Register Data Bits.
These
are the load register data bits.
AR Reload/Capture Register
. The ARRC reload/
capture register is used to hold the auto-reload
value which is automatically loaded into the coun-
ter when overflow occurs.
AR Reload/Capture (ARRC)
Address: D9h
—
Read/Write
Bit 7-0 =
D7-D0
:
Reload/Capture Data Bits
. These
are the Reload/Capture register data bits.
AR Compare Register
. The CP compare register
is used to hold the compare value for the compare
function.
AR Compare Register (ARCP)
Address: DAh
—
Read/Write
Bit 7-0 =
D7-D0
:
Compare Data Bits
. These are
the Compare register data bits.
7
0
PS2
PS1
PS0
D4
SL1
SL0
CC1
CC0
PS2
0
0
0
0
1
1
1
1
PS1
0
0
1
1
0
0
1
1
PS0
0
1
0
1
0
1
0
1
ARPSC Division Ratio
1
2
4
8
16
32
64
128
SL1
X
0
1
SL0
0
1
1
Edge Detection
Disabled
Rising Edge
Falling Edge
CC1
0
0
1
1
CC0
0
1
0
1
Clock Source
F
int
F
int
Divided by 3
ARTIMin Input Clock
Reserved
7
0
D7
D6
D5
D4
D3
D2
D1
D0
7
0
D7
D6
D5
D4
D3
D2
D1
D0
7
0
D7
D6
D5
D4
D3
D2
D1
D0
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參數(shù)描述 |
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| ST62E65CF1 | 制造商:STMicroelectronics 功能描述:IC 8BIT MCU+EEPROM 62E65 DIP20 |
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