參數(shù)資料
型號(hào)： ST6242B
英文描述： 8-BIT MICROCONTROLLER ( MCU ) WITH OTP. ROM. FASTROM. EPROM. LCD DRIVER. EEPROM. A/D CONVERTER AND 64 PINS
中文描述： 8位微控制器（MCU）的與檢察官辦公室。光盤(pán)。 FASTROM。存儲(chǔ)器。液晶顯示驅(qū)動(dòng)程序。 EEPROM中。的A / D轉(zhuǎn)換器和64個(gè)
文件頁(yè)數(shù)： 46/74頁(yè)
文件大小： 733K
代理商： ST6242B
46/74
ST62T46B/E46B
4.4 SERIAL PERIPHERAL INTERFACE (SPI)
The on-chip SPI is an optimized serial synchro-
nous interface that supports a wide range of indus-
try standard SPI specifications. The on-chip SPI is
controlled by small and simple user software to
perform serial data exchange. The serial shift
clock can be implemented either by software (us-
ing the bit-set and bit-reset instructions), with the
on-chip Timer 1 by externally connecting the SPI
clock pin to the timer pin or by directly applying an
external clock to the Scl line.
The peripheral is composed by an 8-bit Data/shift
Register and a 4-bit binary counter while the Sin
pin is the serial shift input and Sout is the serial
shift output. These two lines can be tied together
to implement two wires protocols (I2C-bus, etc).
When data is serialized, the MSB is the first bit. Sin
has to be programmed as input. For serial output
operation Sout has to be programmed as open-
drain output.
The SCL, Sin and Sout SPI clock and data signals
are connected to 3 I/O lines on the same external
pins. With these 3 lines, the SPI can operate in the
following operating modes: Software SPI, S-BUS,
I2C-bus and as a standard serial I/O (clock, data,
enable). An interrupt request can be generated af-
ter eight clock pulses.
Figure 24
shows the SPI
block diagram.
The SCL line clocks, on the falling edge, the shift
register and the counter. To allow SPI operation in
slave mode, the SCL pin must be programmed as
input and an external clock must be supplied to
this pin to drive the SPI peripheral.
In master mode, SCL is programmed as output, a
clock signal must be generated by software to set
and reset the port line.
Figure 24. SPI Block Diagram
Set Res
CLK
RESET
4-Bit Counter
(Q4=High after Clock8)
Data Reg
Direction
I/O Port
8-Bit Data
Shift Register
Reset
Load
DOUT
Output
Enable
8-Bit Tristate Data I/O
RESET
I/O Port
I/O Port
CP
CP
DIN
D0............................D7
to Processor Data Bus
Q4
Q4
OPR Reg.
DIN
SCL
Sin
Sout
SPI Interrupt Disable Register
SPI Data Register
Data Reg
Direction
Data Reg
Direction
DOUT
Write
Read
M
0
1
Interrupt
VR01504
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