參數(shù)資料
型號(hào)： ST52514F3
英文描述： IC MAX 7000 CPLD 128 100-TQFP
中文描述： 8位重癥監(jiān)護(hù)病房，10位ADC。兩個(gè)定時(shí)器/脈寬調(diào)制。 I2C總線。的SPI。脊髓損傷。提供了8K閃存
文件頁(yè)數(shù)： 85/106頁(yè)
文件大小： 1355K
代理商： ST52514F3
Memory can be locked by the user in order to
prevent external undesired operations.
Operations may be performed on data stored in
RAM, allowing direct combination of new inputs
and feedback data. All RAM bytes are used like
Register File.
An additional RAM bench is added to the Program
Memory addressing space in order to allow the
management of the System/User Stacks and user
data storage.
ST52F501L/F502L supply the system stack and
the user stack located in the additional RAM
bench. The user stack can be located anywhere in
the additional RAM by writing the top address in
the configuration registers, in order to avoid
overlap with other data.
Single Voltage Flash allows the user to reprogram
the devices on-board by means of the In Situ
Programming (ISP) feature. It is possible to store in
safe way up to 256 bytes of data in the available
EEPROM memory benches (ST52F502L only).
Permanent data, both in Flash and EEPROM can
be managed by means of the In-Application-
Programming (IAP) feature. Single byte and Page
write
modes
are
supported.
Flexible
write
protection,
of
permanent
data
or
program
instructions, is also available.
The Instruction Set composed of up to 107
instructions allows code compression and high
speed in the program implementation.
A powerful development environment consisting of
a board and software tools allows an easy
configuration and use of ST52F501L/F502L.
The V is u al FI VE s o ftw ar e to ol a ll o ws th e
development and debugging of projects via a user-
friendly graphical interface and optimization of
generated microcode.
Third-party Hardware Emulators and ‘C’ Compiler
ar e av ai la bl e to s p e ed- u p the app li ca tio n
implementation and time-to-market.
1.2 Functional Description
ST52F501L/F502L ICU’s can work in two modes
according to the Vpp signal levels:
s
Memory Programming Mode
s
Working Mode
During Working Mode Vpp must be tied to Vss. To
enter the Memory Programming Mode, the Vpp pin
must be tied to Vdd.
A RESET signal must be applied to the device to
switch from one mode to the other.
1.2.1 Memory Programming Mode.
The ST52F501L/F502L memory is loaded in the
Memory Programming Mode. All instructions and
data are written inside the memory during this
phase.
The Option Bytes are loaded during this phase by
using the programming tools. The Option Bytes
can only be loaded in this phase and cannot be
modified run-time.
Data and commands are transmitted by using the
I2C protocol, implemented using the internal I2C
peripheral. The In-Situ Programming protocol
(ISP) uses the following pins:
s
SDA and SCL for transmission
s
Vpp for entering in the mode
s
RESET for starting the protocol in a stable status
s
Vdd and Vss for the power supply.
The Internal clock is used in this phase.
1.2.2 Working Mode.
The processor starts the working phase following
the instructions, which have been previously
loaded in the first locations of the memory. The first
instruction must be a jump to the first program
instruction, skipping the data (interrupt vectors,
Membership Functions, user data) stored in the
first memory page.
ST52F501L/F502L’s internal structure includes
two computational blocks, the CONTROL UNIT
(CU) and the DATA PROCESSING UNIT (DPU),
which performs boolean functions. The DECISION
PROCESSOR (DP) block cooperates with these
blocks to perform Fuzzy algorithms.
The
DP
can
manage
up
to
340
different
Membership Functions for the antecedent part of
fuzzy rules. The consequent terms of the rules are
“crisp” values (real numbers). The maximum
number of rules that can be defined is limited by
the
dimensions
of
the
standard
algorithm
implemented.
The Program/Data Memory is shared between
Fuzzy
and
standard
algorithms.
Within
this
memory, the user data can be stored both in non
volatile memory as well as in the RAM locations.
The Control Unit (CU) reads information and the
status of the peripherals.
Arithmetic calculus can be performed on these
values by using the internal CU and Register File,
which supports all computations. The
peripheral
inputs can be Fuzzy and/or arithmetic output
values contained in the Register File or Program/
Data Memory.
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