參數(shù)資料
型號(hào): ST52501LK1
英文描述: MAX 7000 CPLD 160 MC 84-PLCC
中文描述: 8位紅外驅(qū)動(dòng)重癥監(jiān)護(hù)病房。定時(shí)器/脈寬調(diào)制。 I2C總線。的SPI。脊髓損傷。低電壓
文件頁數(shù): 47/106頁
文件大小: 1355K
代理商: ST52501LK1
6.4 Power Saving modes
There are two types of Power Saving modes:
WAIT and HALT mode. These conditions may be
entered by using the WAIT or HALT instructions. In
Halt mode only the Programmable Halt mode
Wake-up peripheral (PHW) can run, thus allowing
the exiting from the Halt mode after a programmed
time.
6.4.1 Wait Mode. Wait mode places the ICU in a
low power consumption status by stopping the
CPU. All peripherals and the watchdog remain
active. During WAIT mode the Interrupts are
enabled. The ICU remains in Wait mode until an
Interrupt or a RESET occurs, whereupon the
Program Counter jumps to the interrupt service
routine or, if a Reset occurs, to the beginning of the
user program.
6.4.2 Halt Mode. Halt mode is the lowest ICU
power consumption mode, which is entered by
executing the HALT instruction. The internal
oscillator
is turned
off,
causing
all
internal
processing
to
be
terminated,
including
the
operations of the on-chip peripherals, with the
exception of the PHW (see below) and PDR.
Halt mode cannot be used when the watchdog is
enabled. If the HALT instruction is executed while
the watchdog system is enabled, it will be skipped
without modifying the normal CPU operations.
The ICU can exit Halt mode upon reception of an
NMI, a Port Interrupt, a PHW interrupt (see below)
or a Reset. The internal oscillator (10 MHZ) is
started and a delay period of 128 clock cycles
(12.8
s) is initiated, in order to allow the oscillator
to stabilize and to ensure that recovery has taken
place from the Reset state.
Unless an external quartz clock is configured to be
used, another short count of 4 Internal clock cycles
(400 ns) starts before running the user program.
Otherwise, if an external quartz clock has been
configured to be used, the Option Byte 7
(WAKEUP) is read and another count is started
before running the user program. The count
duration depends on the contents of the Option
Byte 7 (WAKEUP), that works as prescaler,
according to the following formula:
This delay has been introduced in order to ensure
that the oscillator has become stable after it is
restarted.
After the start up delay, by exiting with the NMI, a
Port interrupt or PHW interrupt, the CPU restarts
operations by serving the associated interrupt
routine.
6.5 Programmable Halt mode Wake-up (PHW)
The PHW is a very low consumption Timer,
designed to work even in Halt mode. Its working is
based on a low power 32 kHz Internal Clock that
drives a counter. The end of count can generate an
interrupt or a reset and, if the device is in Halt
mode, a wake-up from this state.
The counter can execute a count from 26 to 216,
corresponding to a time period from 2 ms to 2 s. Up
to six configurable times are possible by setting
Configuration Register 52 (034h) PHW_CR. It also
allows the enabling/disabling or the selection of the
interrupt/reset option (see Register Description).
When the PHW_CR is latched, the counting is
restarted with the new value.
This peripheral has been designed to operate a
wake-up from Halt mode at programmed time;
nevertheless it can be used as a normal timer.
Figure 6.4 WAIT Flow Chart
Delay
128
WAKEUP
1
+
() Tclk
×
=
OSCILLATOR
PERIPHERALS CLOCK
CPU CLOCK
INTERRUPTS
ON
OFF
ENAB.
WAIT ISTRUCTION
RESET
INTERRUPT
YES
NO
CPU CLOCK
ON
PROGRAM COUNTER RESET
NO
JUMP TO INT. ROUTINE
CPU CLOCK
ON
NORMAL PROGRAM FLOW
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