參數資料
型號: ST52501LG3
英文描述: MAX 7000 CPLD 128 MC 100-TQFP
中文描述: 8位紅外驅動重癥監(jiān)護病房。定時器/脈寬調制。 I2C總線。的SPI。脊髓損傷。低電壓
文件頁數: 71/106頁
文件大?。?/td> 1355K
代理商: ST52501LG3
11 PWM/TIMERS AND IR DRIVER
11.1 Introduction
ST52F501L/F502L offers two on-chip PWM/Timer
peripherals. All ST52F501L/F502L PWM/Timers
have the same internal structure. The timer
consists
of
a
8-bit
counter
with
a
16-bit
programmable Prescaler, giving a maximum count
of 224 (see Figure 11.1).
Each timer has two different working modes, which
can be selected by setting the correspondent bit
TxMOD
of
the
PWMx_CR1
Configuration
Register: Timer Mode and PWM (Pulse Width
Modulation) Mode. In addition the PWM/Timer 1
output can be used as input of the IR Driver (see
below) to perform digital modulation of the digital
carrier generated by the PWM/Timer 1 itself.
All the Timers have Autoreload Functions; in PWM
Mode the reload value can be set by the user.
Each timer output is available on the apposite
external pins configured in Alternate Function and
in one of the Output modes. The outputs of both
PWM/Timers can be synchronized and combined
in OR, AND, XOR and NOT in order to generate
complex wave modulation.
PWM/Timer 0 can also use external START/STOP
signals in order to perform Input capture and
Output compare, external RESET signal, and
external CLOCK to count external events: TSTRT,
TRES and TCLK pins. In addition, the START/
STOP and RESET signals have configurable
polarity (falling or rising edge).
Remark: To use TRES, TSTRT, TCLK external
signals the related pins must be configured in
Alternate Function and in one of Input modes.
For each timer, the contents of the 8-bit counter
are incremented on the Rising Edge of the 16-bit
prescaler output (PRESCOUT) and it can be read
at any instant of the counting phase by accessing
the Input Register PWMx_COUNT_IN.
Figure 11.1 PWM/Timer Counter block diagram
The Input Register PWMx_CAPTURE stores the
counter value after the last Stop signal (only Timer
Mode). The counter value is not stored after a
Reset Signal.
The peripheral status can also be read from the
Input Registers (one for each Timer). These
registers
report
START/STOP,
SET/RESET
status, TxOUT signal and the counter overflow
flag. This last signal is set after the first EOC and it
is reset by a Timer RESET (internal or external).
11.2 Timer Mode
Timer Mode is selected writing 0 in the TxMOD bit.
Each Timer requires three signals: Timer Clock
(TMRCLKx), Timer Reset (TxRES) and Timer Start
(TxSTRT) (see Figure 11.1). Each of these signals
can be generated internally, and/or externally only
for Timer 0, by using TRES, TSTRT and TCLK
pins.
The Prescaler output (PRESCOUT) increments
the Counter value on the rising edge. PRESCOUT
is obtained from the internal clock signal (CLKM)
or, only for Timer 0, from the external signal
provided on the apposite pin.
Note: The external clock signal applied on the
TCLK pin must have a frequency that is at least two
times smaller than the internal master clock.
The prescaler output period can be selected by
setting the TxPRESC bits with one of the 17
division factors available. TMRCLK frequency is
divided by a factor equal to the power of two of the
prescaler values (up to 216).
TxRES resets the content of the 8-bit counter to
zero. It is generated by writing 0 in the TxRES bit
of the PWMx_CR1 Configuration Register and/or it
can be driven by the TRES pin if configured (only
Timer0).
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 14
BIT 15
BIT 3
BIT 0
BIT 1
BIT 2
BIT 6
BIT 4
BIT 5
BIT 7
17 - 1 MULTIPLEXER
16-BIT PRESCALER
8-BIT COUNTER
PRESCx
CLKM
TMRCLK
TxRES
TxSTRT
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