參數(shù)資料
型號(hào): ST40RA166XH6
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 166 MHz, RISC PROCESSOR, PBGA372
封裝: 27 X 27 MM, 2.33 MM HEIGHT, PLASTIC, BGA-372
文件頁數(shù): 21/92頁
文件大?。?/td> 2129K
代理商: ST40RA166XH6
28/92
ST40RA
5 System configuration
5.3
Interrupt mapping
For full details on the interrupt controller see ST40 System Architecture Manual Volume 1:System.
The mapping of the CPU interrupts is described in Section 5.3.1, Section 5.3.2 and Section 5.3.3.
Note:
Some INTEVT codes are shown as reserved in Table 6 and therefore cannot be generated by this
device.
5.3.1
ST40 core interrupt allocation
The allocation of core interrupts is as shown in Table 6.
Table 6: ST40 core interrupt allocation (page 1 of 2)
Interrupt source
INTEVT
code
Interrupt priority
IPR
bit numbers
Priority
within IPR
setting unit
Value
Initial value
NMI
0x1C0
16
-
IRL
level
encoding
IRL3–IRL0 = F
0x200
15
-
IRL3–IRL0
= E
0x220
14
-
IRL3–IRL0
= D
0x240
13
-
IRL3–IRL0
= C
0x260
12
-
IRL3–IRL0
= B
0x280
11
-
IRL3–IRL0
= A
0x2A0
10
-
IRL3–IRL0
= 90x2C0
9
-
IRL3–IRL0
= 80x2E0
8
-
IRL3–IRL0
= 70x300
7
-
IRL3–IRL0
= 60x320
6
-
IRL3–IRL0
= 50x340
5
-
IRL3–IRL0
= 40x360
4
-
IRL3–IRL0
= 30x380
3
-
IRL3–IRL0
= 20x3A0
2
-
IRL3–IRL0
= 10x3C0
1
-
IRL
independent
encoding
IRL0
0x240
15 to 0
13
IPRD[15:12]
-
IRL1
0x2A0
15 to 0
10
IPRD[11:8]
-
IRL2
0x300
15 to 0
7
IPRD[7:4]
-
IRL3
0x360
15 to 0
4
IPRD[3:0]
-
H-UDI
0x600
15 to 0
0
IPRC[3:0]
-
TMU0
TUNI0
0x400
15 to 0
0
IPRA[15:12]
-
TMU1
TUNI1
0x420
0 to 15
0
IPRA[11:8]
-
TMU2
TUNI2
0x440
0 to 15
0
IPRA[7:4]
High
TICPI2
0x460
Low
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