參數(shù)資料
型號: ST24LW21M6
英文描述: Cyclone II FPGA 15K FBGA-256
中文描述: I2C串行EEPROM的
文件頁數(shù): 14/21頁
文件大?。?/td> 152K
代理商: ST24LW21M6
Page Write.
The Page Write mode allows up to 8
bytes to be written in a single write cycle, provided
that they are all located in the same ’row’ in the
memory: that is the most significant memory ad-
dress bits are the same. The master sends from
one up to 8 bytes of data, which are each acknow-
ledged by the memory.
After each byte is transfered, the internal byte
address counter (3 least significant bits only) is
incremented. The transfer is terminated by the
master generating a STOP condition. Care must be
taken to avoid address counter ’roll-over’ which
could result in data being overwritten. Note that, for
any write mode, the generation by the master of the
STOP condition starts the internal memory pro-
gram cycle. All inputs are disabled until the comple-
tion of this cycle and the memory will not respond
to any request.
Minimizing System Delays by Polling On ACK
.
During the internal write cycle, the memory discon-
nects itself from the bus in order to copy the data
from the internal latches to the memory cells. The
maximum value of the write time (t
W
) is given in the
AC Characteristics table, since the typical time is
shorter, the time seen by the system may be re-
duced by an ACK polling sequence issued by the
master. The sequence is as follows:
– Initial condition: a Write is in progress (see Fig-
ure 10).
– Step 1: the Master issues a START condition
followed by a Device Select byte (1st byte of
the new instruction).
S
S
BYTE WRITE
DEV SEL
BYTE ADDR
DATA IN
S
PAGE WRITE
DEV SEL
BYTE ADDR
DATA IN 1
DATA IN 2
AI01893
S
DATA IN N
ACK
ACK
ACK
R/W
ACK
ACK
ACK
R/W
ACK
ACK
VCLK/WC
VCLK/WC
Figure 11. Write Modes Sequence
14/21
ST24LC21B, ST24LW21, ST24FC21, ST24FW21
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