參數(shù)資料
型號： ST16C654IQ100
廠商： EXAR CORP
元件分類： 微控制器/微處理器
英文描述： 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
中文描述： 4 CHANNEL(S), 1.5M bps, SERIAL COMM CONTROLLER, PQFP100
封裝： 14 X 20 MM, PLASTIC, QFP-100
文件頁數(shù)： 25/51頁
文件大?。?/td> 968K
代理商： ST16C654IQ100
ST16C654/654D
2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
REV. 5.0.0
25
4.3.2
When FCR BIT-0 equals a logic 1 for FIFO enable; resetting IER bits 0-3 enables the ST16C654 in the FIFO
polled mode of operation. Since the receiver and transmitter have separate bits in the LSR either or both can
be used in the polled mode by selecting respective transmit or receive control bit(s).
A.
4 )(0
5 6 2(23%
B.
4 )(
C.
4 )( 7 !
!
D.
4 )( 5 "%
E.
4 )( " 2(23 "%
F.
4 )(8
6
IER[0]: RHR Interrupt Enable
The receive data ready interrupt will be issued when RHR has a data character in the non-FIFO mode or when
the receive FIFO has reached the programmed trigger level in the FIFO mode.
Logic 0 = Disable the receive data ready interrupt (default).
Logic 1 = Enable the receiver data ready interrupt.
IER[1]: THR Interrupt Enable
This bit enables the Transmit Ready interrupt which is issued whenever the THR becomes empty in the non-
FIFO mode or when data in the FIFO falls below the programmed trigger level in the FIFO mode. If the THR is
empty when this bit is enabled, an interrupt will be generated.
Logic 0 = Disable Transmit Ready interrupt (default).
Logic 1 = Enable Transmit Ready interrupt.
IER[2]: Receive Line Status Interrupt Enable
If any of the LSR register bits 1, 2, 3 or 4 is a logic 1, it will generate an interrupt to inform the host controller
about the error status of the current data byte in FIFO. LSR bit-1 generates an interrupt immediately when an
overrun occurs. LSR bits 2-4 generate an interrupt when the character in the RHR has an error.
Logic 0 = Disable the receiver line status interrupt (default).
Logic 1 = Enable the receiver line status interrupt.
IER[3]: Modem Status Interrupt Enable
Logic 0 = Disable the modem status register interrupt (default).
Logic 1 = Enable the modem status register interrupt.
IER[4]: Sleep Mode Enable (requires EFR[4] = 1)
Logic 0 = Disable Sleep Mode (default).
Logic 1 = Enable Sleep Mode. See Sleep Mode section for further details.
IER[5]: Xoff Interrupt Enable (requires EFR[4]=1)
Logic 0 = Disable the software flow control, receive Xoff interrupt. (default)
Logic 1 = Enable the software flow control, receive Xoff interrupt. See Software Flow Control section for
details.
IER[6]: RTS# Output Interrupt Enable (requires EFR[4]=1)
Logic 0 = Disable the RTS# interrupt (default).
Logic 1 = Enable the RTS# interrupt. The UART issues an interrupt when the RTS# pin makes a transition
from low to high (if enabled by EFR bit-6).
IER versus Receive/Transmit FIFO Polled Mode Operation
2(23 "
%
5/ ! %
2(23%
相關(guān)PDF資料
PDF描述
ST16C654IQ64 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
ST16KF74 Microcontroller
ST16LF74 Microcontroller
ST16MF74 Microcontroller
ST16NF74 Microcontroller
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ST16C654IQ100-F 功能描述:UART 接口集成電路 QUAD UARTW/64BYTE FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
ST16C654IQ100TR-F 制造商:Exar Corporation 功能描述:UART 4-CH 64Byte FIFO 3.3V/5V 100-Pin LQFP T/R 制造商:Exar Corporation 功能描述:ST16C654IQ100TR-F
ST16C654IQ64 制造商:Exar Corporation 功能描述:UART, 64 Pin, Plastic, QFP
ST16C654IQ64-F 功能描述:UART 接口集成電路 QUAD UARTW/64BYTE FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
ST16C654IQ64-F 制造商:Exar Corporation 功能描述:IC QUAD UART 1.5MBPS 5.5V 64-LQFP 制造商:Exar Corporation 功能描述:IC, QUAD UART, 1.5MBPS, 5.5V, 64-LQFP
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*